Blog Review: Aug. 26

By Jesse Allen - 26 Aug, 2015 - Comments: 0

Synopsys' Marc Greenberg attended IDF and learned more about the newly announced Intel/Micron 3D XPoint memory technology named Optane including initial ship dates and some implementation details. In concluding his analysis of the 2014 Functional Verification Study, Mentor's Harry Foster reveals an unexpected finding about design size and respins. How do you keep your power grid from bein... » read more

Inside The 5G Smartphone

By Mark LaPedus - 20 Aug, 2015 - Comments: 3

Amid a slowdown in the cell phone business, the market is heating up for perhaps the next big thing in wireless—5th generation mobile networks or 5G. In fact, major carriers, chipmakers and telecom equipment vendors are all rushing to get a piece of the action in 5G, which is the follow-on to the current wireless standard known as 4G or long-term evolution (LTE). Intel, Samsung and Qualcom... » read more

Tech Talk: DDR4

By Ed Sperling - 17 Aug, 2015 - Comments: 1

Rambus' Ely Tsern digs into the challenges in integrating DDR4 compared with DDR3 and why it will get even more difficult over the next few iterations. [youtube vid=2M6vFweaZ-M] » read more

Fundamental Shifts In Chip Business

By Ed Sperling - 17 Aug, 2015 - Comments: 3

Shifting business models, acquisitions, minority investments and increasing uncertainty are creating fundamental shifts in the semiconductor industry that could redefine who is successful in which markets for years to come. The announcement today that [getentity id="22671" e_name="Rambus"] is developing memory controller chips, expanding its business beyond just creating IP for the memory an... » read more

Don’t Let The Headlines Trick You

By Loren Shalinsky - 09 Jul, 2015 - Comments: 0

This is the time of year when reports get issued summarizing the sales results of the server market in the first quarter. As a way of grabbing attention, many of the headlines will mention that the results of the first quarter are below those of the fourth quarter, bringing to mind all sorts of doomsday scenarios. Don’t be fooled. In many industries, sales exhibit a large seasonal compo... » read more

More Data, Different Approaches

By Ed Sperling - 25 Jun, 2015 - Comments: 0

Scaling, rising complexity, and integration are all contributing to an explosion in data, from initial design to physical layout to verification and into the manufacturing phase. Now the question is what to do with all of that data. For SoC designs, that data is critical for identifying real and potential problems. It also allows verification engineers working the back end of the design flow... » read more

How Is Your HBM Memory?

By Frank Ferro - 14 May, 2015 - Comments: 0

The seemingly countless applications used every day requiring web access (social media, streaming video, games, etc.) are not only driving the need to store a tremendous amount of data, but also driving the need to access this data with as little delay as possible. Add to this list the growing number of connected devices (IoT), and you can see why changes in the data center are needed, in parti... » read more

Architecturally Optimizing Memory Bandwidth

By Ann Mutschler - 27 Mar, 2015 - Comments: 0

Making sure that an SoC’s [getkc id="22" kc_name="memory"] bandwidth is optimized is a crucial part of the design process today given its significance toward overall system performance. There are many ways to approach this issue, and all of them can have a direct bearing on the competitiveness of a chip in terms of both power and performance. So where should you start? “Number one, c... » read more

DDR4 Board Design And Signal Integrity Verification Challenges

By Mentor, a Siemens Business - 25 Mar, 2015 - Comments: 0

This paper, originally presented at DesignCon and nominated for a best paper award, includes an investigation of DDR4's Pseudo Open Drain driver and what its use means for power consumption and Vref levels for the receivers. This paper also examines a DDR4 system design example and the need for simulating with IBIS power aware models versus transistor level models for Simultaneous Switching ... » read more

Higher Frequencies Mean More Memory

By Ann Mutschler - 16 Jan, 2015 - Comments: 0

As SoCs get more complex, whether due to higher frequencies or adding more functionality, there is a spillover effect on bandwidth, [getkc id="22" kc_name="memory"] and power. There is no simple way to just turn up the clock frequency in a complex [getkc id="81" kc_name="SoC"]. That relatively straightforward objective will likely require more power domains, more cores, more ways to move sig... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?