tag: DDR4

Don’t Let The Headlines Trick You
By Loren Shalinsky - 09 Jul, 2015 - Comments: 0

This is the time of year when reports get issued summarizing the sales results of the server market in the first quarter. As a way of grabbing attention, many of the headlines will mention that the results of the first quarter are below those of the fourth quarter, bringing to mind all sorts of doomsday scenarios. Don’t be fooled. In many industries, sales exhibit a large seasonal compo... » read more

More Data, Different Approaches
By Ed Sperling - 25 Jun, 2015 - Comments: 0

Scaling, rising complexity, and integration are all contributing to an explosion in data, from initial design to physical layout to verification and into the manufacturing phase. Now the question is what to do with all of that data. For SoC designs, that data is critical for identifying real and potential problems. It also allows verification engineers working the back end of the design flow... » read more

How Is Your HBM Memory?
By Frank Ferro - 14 May, 2015 - Comments: 0

The seemingly countless applications used every day requiring web access (social media, streaming video, games, etc.) are not only driving the need to store a tremendous amount of data, but also driving the need to access this data with as little delay as possible. Add to this list the growing number of connected devices (IoT), and you can see why changes in the data center are needed, in parti... » read more

Architecturally Optimizing Memory Bandwidth
By Ann Mutschler - 27 Mar, 2015 - Comments: 0

Making sure that an SoC’s [getkc id="22" kc_name="memory"] bandwidth is optimized is a crucial part of the design process today given its significance toward overall system performance. There are many ways to approach this issue, and all of them can have a direct bearing on the competitiveness of a chip in terms of both power and performance. So where should you start? “Number one, c... » read more

DDR4 Board Design And Signal Integrity Verification Challenges
By Mentor, a Siemens Business - 25 Mar, 2015 - Comments: 0

This paper, originally presented at DesignCon and nominated for a best paper award, includes an investigation of DDR4's Pseudo Open Drain driver and what its use means for power consumption and Vref levels for the receivers. This paper also examines a DDR4 system design example and the need for simulating with IBIS power aware models versus transistor level models for Simultaneous Switching ... » read more

Higher Frequencies Mean More Memory
By Ann Mutschler - 16 Jan, 2015 - Comments: 0

As SoCs get more complex, whether due to higher frequencies or adding more functionality, there is a spillover effect on bandwidth, [getkc id="22" kc_name="memory"] and power. There is no simple way to just turn up the clock frequency in a complex [getkc id="81" kc_name="SoC"]. That relatively straightforward objective will likely require more power domains, more cores, more ways to move sig... » read more

Digital TV: The Need For Speed
By Loren Shalinsky - 15 Jan, 2015 - Comments: 1

With CES just finishing up, I wanted to take a closer look at the changes in the digital TV market, and what affect those changes have on high performance memory and serial links. Just five years ago, the United States made the transition from analog to digital television. At the time, standard definition digital TV was common, with screens that contained 345 thousand pixels per frame. Recen... » read more

Hybrid Memory Cube – Ready For Prime Time
By Manohar Ayyagiri - 20 Nov, 2014 - Comments: 0

With the release this week of Hybrid Memory Cube (HMC) 2.0, designers can get their hands on mature, standards-based IP that can be used to significantly scale the performance of servers and data centers. HMC offers bandwidths up to 320 GB/s – 12X that of standard memory solutions like DDR4 – while consuming significantly less power. These benefits are too significant to ignore for ASIC, So... » read more

Memory Directions Uncertain
By Brian Bailey - 28 Oct, 2014 - Comments: 1

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

The Week In Review: Design
By Ed Sperling - 17 Oct, 2014 - Comments: 0

Legal Mentor Graphics won a $36 million award plus royalties stemming from a patent infringement case involving EVE (Emulation & Verification Engineering), an emulation company that was purchased by Synopsys in 2012. A U.S. District Court jury in the District of Oregon found that EVE had directly and indirectly infringed on a 2001 patent entitled "Method and apparatus for gate-level simula... » read more

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