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DDR4 Board Design And Signal Integrity Verification Challenges

A deep dive into power consumption and Vref levels, and best practices for simulating Simultaneous Switch Noise characterization.

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This paper, originally presented at DesignCon and nominated for a best paper award, includes an investigation of DDR4’s Pseudo Open Drain driver and what its use means for power consumption and Vref levels for the receivers.

This paper also examines a DDR4 system design example and the need for simulating with IBIS power aware models versus transistor level models for Simultaneous Switching Noise characterization. To read more, click here.



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