tag: DDR4

Will There Be A DDR5?
By Ed Sperling - 10 Oct, 2014 - Comments: 1

DDR4 rollouts have begun. And in the DRAM world that begs the question, 'What comes next?' The answer isn't so obvious. While there have been suggestions inside of JEDEC — the Joint Electron Device Engineering Council, which has overseen the standards for double-data-rate synchronous DRAM — to develop a DDR5 standard, it's not the only solution being considered. And in the minds of some... » read more

Driving Memory Beyond DDR4
By Frank Ferro - 09 Oct, 2014 - Comments: 0

While attending recent technology trade shows, the Intel Developer’s Forum (IDF) in August and last week’s ARM TechCon, I participated in many interesting discussions around server performance, power consumption, memory bandwidth and capacity. The race to introduce higher-performing servers that consume less power is fueled by the growing demand for new applications in the enterprise, commu... » read more

Memory Directions Uncertain
By Brian Bailey - 09 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

Collaboration Accelerates Moore’s Law
By Joe Gullo - 11 Sep, 2014 - Comments: 0

Moore's Law dictates that the number of transistors in dense, integrated circuits will double approximately every two years. Maintaining this pace of scaling, however, has become increasingly difficult given the ever-increasing complexity inherent with new chip starts. Additionally, the cost of using leading-edge process technology is prohibitively expensive. As a result, collaboration amon... » read more

Improving Yield Of 2.5D Designs
By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

Blog Review: March 26
By Ed Sperling - 26 Mar, 2014 - Comments: 0

Synopsys’ Eric Huang has discovered a video of Superman using a GoPro camera (scroll down to bottom of page). So this is what it’s like to stop bullets with your hand. Cadence’s Tom Hackett zeroes in on mobile interfaces in a video—SoC fabric, memory and chip-to-chip. Nice whiteboard drawing. Mentor’s Anil Khanna looks at a methodology for developing high-performance embedded so... » read more

Memory Architectures Undergo Changes
By Ed Sperling - 22 Aug, 2013 - Comments: 0

By Ed Sperling Memory architectures are taking some new twists. Fueled by multi-core and multiple processors, as well as some speed bumps using existing technology, SoC makers are beginning to rethink how to architect, model and assemble memory to improve speed, lower power and reduce cost. What’s unusual about all of this is that it doesn’t rely on new technology, although there certai... » read more

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