Blog Review: April 17

By Jesse Allen - 17 Apr, 2019 - Comments: 0

In a video, Mentor's Colin Walls digs into power management in embedded software with a particular look at the Power Pyramid model. Synopsys' Taylor Armerding checks out the state of application security at this year's RSA and finds that while organizations are paying attention to security through training and dedicated teams, roadblocks still remain. Cadence's Paul McLellan considers how... » read more

Exascale Emulation Debug Challenges

By Ribhu Mittal - 11 Apr, 2019 - Comments: 0

For years, semiconductor industry surveys have shown that functional verification is the dominant phase in chip development and that debug is the most time-consuming task for verification. The problem is getting worse in today’s era of exascale debug, in which software applications drive tests of more than a billion cycles run in emulation on designs of more than a billion gates. System-on-ch... » read more

From AI Algorithm To Implementation

By Brian Bailey - 10 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Utilizing More Data To Improve Chip Design

By Ann Mutschler - 28 Mar, 2019 - Comments: 0

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

Debug Changes At Advanced Nodes

By Ed Sperling - 27 Mar, 2019 - Comments: 0

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a commensurate amount of software complexity. The key is how to maintain or reduce time to market, and that requires a different way of approaching the problem. » read more

The Challenge Of RISC-V Compliance

By Brian Bailey - 28 Feb, 2019 - Comments: 0

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

Can Debug Be Tamed?

By Brian Bailey - 28 Feb, 2019 - Comments: 0

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Reverse Debug

By Ed Sperling - 28 Feb, 2019 - Comments: 0

Chun Chan, product applications engineering director at Synopsys, talks with Semiconductor Engineering about testbench debug and how adding time markers can speed time to signoff. https://youtu.be/tx_89M1bq3Q » read more

A Simplified Way to Debug IIP Designs and SoC

By Synopsys - 30 Jan, 2019 - Comments: 0

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

Taming Concurrency

By Brian Bailey - 17 Jan, 2019 - Comments: 2

Concurrency adds complexity for which the industry lacks appropriate tools, and the problem has grown to the point where errors can creep into designs with no easy or consistent way to detect them. In the past, when chips were essentially a single pipeline, this wasn't a problem. In fact, the early pioneers of EDA created a suitable language to describe and contain the necessary concurrency ... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: debug