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Speed Up P2P Resistance Debugging With Selective Highlighting

Use filters to remove layout data that is unused and unnecessary to speed identification of high-resistance problem areas.

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Point-to-point (P2P) resistance simulation calculates the effective parasitic resistance from one or more specified points (sources) to another set of points (sinks) on an integrated circuit (IC) layout. The results of these simulations are a key component in the verification of the robustness and reliability of IC layout interconnect—designers must have this information to accurately perform reliability checks such as full-path electrostatic discharge (ESD) analysis.

ESD checks help ensure the proper implementation of IC ESD protection circuitry, which protects the circuit core from a real-world ESD event. Ensuring that the layout interconnect parasitic resistance does not significantly impact the function of the protection circuitry is a critical part of such checks. To determine that an ESD circuit is reliable and robust, P2P rule checks define certain resistance thresholds that must not be exceeded by the net layout interconnect of an ESD path. When these resistance thresholds are exceeded by some nets in the design (as reported by a P2P simulation), designers must debug the layout to identify which portion or portions of the net layout are contributing the most to the higher effective P2P resistance.

However, with the growth in IC layout design complexity, debugging P2P resistance violations is becoming more and more time-consuming. One crucial element in the debug process is the ability to easily highlight and inspect relevant layout nets in both the P2P debug tool that reports the violation and the layout design viewer that allows designers to fix the layout. P2P check results, such as those for full-path ESD checks, often contain power and ground nets whose interconnect can span the entire chip layout. The large size of these nets means significant time is consumed loading the highlighted power and ground net polygons from the debug environment to the design environment.

In an effort to save this time, layout designers often avoid highlighting and inspecting these larger power and ground nets altogether. They simply use other, more advanced stages in the debug flow, such as running additional simulations that are not typically required for simpler layout errors. Unfortunately, taking this approach ultimately results in more overall time spent debugging these P2P errors. The right answer? Highlight only what is needed for debugging.

P2P resistance debugging
In P2P resistance debugging, the first step is to examine the net in a layout viewer. This review enables designers to quickly catch more obvious routing mistakes, and to identify areas where parasitic resistance can be reduced. Depending on how familiar designers are with the layout design, they may be able to use a simple visual layout inspection to identify locations where the addition of more parallel routing paths or vias could potentially reduce the resistance in an area highlighted by a P2P violation. The intuitive approach is to trace through the design in the manner that the current would flow through the net layout. To effectively trace through the net layer by layer, designers must be able to inspect the routing and via layers separately.

For smaller and simpler signal nets, setting up this kind of flow usually doesn’t take much time or many resources. However, for large and/or complex power or ground nets, computing resource consumption and highlight loading times quickly become significant factors. Filtering out unnecessary highlight data from the resistance simulation results to minimize resource usage and loading time is critical to improving debugging flow efficiency for these larger nets.

Generally, in P2P simulations of larger or more complex networks, the shortest current path has the highest probability of being in the vicinity of the source and sink points. The routing of a power or ground net layout further away from the sources and sinks is probably irrelevant in the context of a single P2P error result, meaning highlighting the entire power or ground net may not be necessary. Consequently, one effective way to reduce highlight loading time for power and ground nets, and still enable designers to inspect the portion of the P2P result net that is the most likely contributor to the P2P resistance in a layer-by-layer process, is to highlight only that part of the net that is relevant to the P2P result being inspected.

Selecting relevant net area with filters
Designers normally view and debug verification and simulation results using a results viewer interface. These electronic design automation (EDA) tools typically provide graphical debugging capabilities that have been designed to support an easy-to-use, intuitive debugging process that minimizes the time designers must spend locating and fixing design issues. To illustrate the use of the filtering technique, we’re using the Calibre RVE results viewer from Mentor, a Siemens business.

The Calibre RVE results viewer enables designers to select from three filters to limit the scope of layout net highlights, as shown in Figure 1.

  • The layer filter creates a global filter that defines which layers are highlighted (if nets are highlighted by layer to the design environment).
  • The device filter specifies the type of devices that will or will not show up (when devices are highlighted on a net to the layout)
  • The window filter specifies an area in the layout viewer that limits the layout highlights to only those polygons that are within the borders of the set bounding box. Polygons touching the border of the bounding box are only partially highlighted (up to that border).

Setting a global highlight filter on a P2P resistance simulation results database restricts all the layout highlights made in the debugging tool to a specified region in the layout viewer, and also supports net highlighting on separate layers. The global highlight window filter provides control over how much data will be highlighted, while the highlight by layer option allows the same detailed layout inspection that is available for smaller signal nets.


Figure 1. Global window, device, and layer filters let designers define how much they need to view during debugging.

Designers use a window filter when they want to limit the net highlight to a relevant area of the layout. They use the P2P simulation result source and sink points to determine the relevant area, and where the highlight window should be set (Figure 2).


Figure 2. Selected highlight area within P2P results.

For smaller nets, the designer typically highlights the simulation results with the sources and sinks, and directly highlights the entire net by its individual layers. This enables the designer to see the locations of the source and sinks, as well as what the net routing looks like. Now the designer can navigate to the P2P simulation result of interest, generating a view similar to that shown in Figure 2.

Once the P2P result is highlighted, the net is highlighted to provide context. The default highlight is the entire net on one layer. In the Calibre RVE results viewer, a context menu provides designers with alternative highlighting options. For example, selecting the Highlight on Layer option lets designers specify which metal and via layers of the net to highlight in the layout view (Figure 3). In this option, each included layer is highlighted as a separate layer, enabling a layer-by-layer inspection of the net.


Figure 3. Highlighting options enable designers to customize highlighted selections.

However, even if the highlight size is already limited by the exclusion of some or most of the layers, there may still be too much data to quickly highlight large power and ground nets. For large nets, the window filter must be set before highlighting the net itself. Designers can use the window filter and set a bounding box that includes both the P2P result highlight and the sources and sinks shown in Figure 2 to set up a global area filter that includes only the net polygons that are relevant to the highlighted P2P result.

Once this global window filter is set, it takes precedence over all other highlights performed in the session. Now, even larger power and ground nets can  be highlighted without incurring long load times, just like the smaller, more manageable nets. Figure 4 shows a net that was highlighted using the highlight on layer option within the global window filter area.


Figure 4. Highlight by layer in filtered area.

The combination of a global window filter and the use of the local highlight by layer option enables designers to highlight and inspect large nets without loading the highlight data for the entire net layout. Designers have the flexibility to modify the window filter as needed, either to see different P2P results, or to expand or reduce the highlight for the current result

Conclusion
Highlighting entire power and ground nets in the layout design is often a time-consuming process. However, combining these highlights with visual layout net inspection can be a highly efficient means of reducing time spent in the P2P resistance debug flow, making it a valuable first step towards correcting P2P violations. To enforce this efficiency, designers must be able to limit the scope of the data being highlighted for review. When debugging P2P violations in large power and ground nets, using filters in the debugging environment lets designers filter out layout data that is unused and unnecessary during highlighting. This approach not only drastically reduces highlight load times, but also enables designers to quickly locate more obvious high resistance problem areas using visual net inspection, reducing the use of both time and resources, while delivering the accuracy needed to ensure reliable, robust designs.

For more information, download our new whitepaper, Faster P2P Resistance Debugging of Supply Nets.

 



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