A PIM Architecture That Supports Floating Point-Precision Computations Within The Memory Chip

A technical paper titled “FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications” was published by researchers at Rochester Institute of Technology and George Mason University. Abstract: "Processing-in-Memory (PIM) has shown great potential for a wide range of data-driven applications, especially Deep Learnin... » read more

Improving Image Resolution At The Edge

How much cameras see depends on how accurately the images are rendered and classified. The higher the resolution, the greater the accuracy. But higher resolution also requires significantly more computation, and it requires flexibility in the design to be able to adapt to new algorithms and network models. Jeremy Roberson, technical director and software architect for AI/ML at Flex Logix, talks... » read more

RL-Guided Detailed Routing Framework for Advanced Custom Circuits

A technical paper titled "Reinforcement Learning Guided Detailed Routing for Custom Circuits" was published by researchers at UT Austin, Princeton University, and NVIDIA. "This paper presents a novel detailed routing framework for custom circuits that leverages deep reinforcement learning to optimize routing patterns while considering custom routing constraints and industrial design rules. C... » read more

Hyperscale HW Optimized Neural Architecture Search (Google)

A new technical paper titled "Hyperscale Hardware Optimized Neural Architecture Search" was published by researchers at Google, Apple, and Waymo. "This paper introduces the first Hyperscale Hardware Optimized Neural Architecture Search (H2O-NAS) to automatically design accurate and performant machine learning models tailored to the underlying hardware architecture. H2O-NAS consists of three ... » read more

3D-IC: Operator Learning Framework For Ultra-Fast 3D Chip Thermal Prediction Under Multiple Chip Design Configurations

A new technical paper titled "DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design" was published (preprint) by researchers at UCSB and Cadence. Abstract "Thermal issue is a major concern in 3D integrated circuit (IC) design. Thermal optimization of 3D IC often requires massive expensive PDE simulations. Neural network-based thermal prediction models can perform ... » read more

Co-Design View of Cross-Bar Based Compute-In-Memory

A new review paper titled "Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective" was published by researchers at Argonne National Lab, Purdue University, and Indian Institute of Technology Madras. "With an over-arching co-design viewpoint, this review assesses the use of cross-bar based CIM for neural networks, connecting the material proper... » read more

More Accurate And Detailed Analysis of Semiconductor Defects In SEM Images Using SEMI-PointRend

A technical paper titled "SEMI-PointRend: Improved Semiconductor Wafer Defect Classification and Segmentation as Rendering" was published (preprint) by researchers at imec, University of Ulsan, and KU Leuven. Abstract: "In this study, we applied the PointRend (Point-based Rendering) method to semiconductor defect segmentation. PointRend is an iterative segmentation algorithm inspired by ima... » read more

Agile HW Design: Fully Automatic Equivalence Checking Workflow

A new technical paper titled "An Equivalence Checking Framework for Agile Hardware Design" was published by researchers at Portland State University and Intel. Abstract "Agile hardware design enables designers to produce new design iterations efficiently. Equivalence checking is critical in ensuring that a new design iteration conforms to its specification. In this paper, we introduce an eq... » read more

ISA and Microarchitecture Extensions Over Dense Matrix Engines to Support Flexible Structured Sparsity for CPUs (Georgia Tech, Intel Labs)

A technical paper titled "VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs" was published (preprint) by researchers at Georgia Tech and Intel Labs. Abstract: "Deep Learning (DL) acceleration support in CPUs has recently gained a lot of traction, with several companies (Arm, Intel, IBM) announcing products with specialized matrix engines accessible v... » read more

Review of Tools & Techniques for DL Edge Inference

A new technical paper titled "Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review" was published in "Proceedings of the IEEE" by researchers at University of Missouri and Texas Tech University. Abstract: Successful integration of deep neural networks (DNNs) or deep learning (DL) has resulted in breakthroughs in many areas. However, deploying thes... » read more

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