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A graph placement methodology for fast chip design


Abstract "Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method autom... » read more

System Bits: Nov. 6


Keeping data private To preserve privacy during data collection from the Internet, Stanford University researchers have developed a new technique that maintains personal privacy given that the many devices part of our daily lives collect information about how we use them. Stanford computer scientists Dan Boneh and Henry Corrigan-Gibbs created the Prio method for keeping collected data priva... » read more