Custom Compiler Technology Highlights from 2022.06 Release

Weikai Sun, VP of Engineering at Synopsys, highlights the key technologies in Custom Compiler’s latest release. He shows how Synopsys’ innovative solutions for design closure, layout automation and emerging applications are increasing the productivity of design teams. Click here to access the  video white paper. » read more

RF/Microwave EDA Software Design Flow Considerations For PA MMIC Design

In this white paper, a gallium arsenide (GaAs) pseudomorphic high-electron mobility transistor (pHEMT) power amplifier (PA) design approach is examined from a systems perspective. It highlights the design flow and its essential features for most PA design projects by illustrating a simple Class A GaAs pHEMT monolithic microwave IC (MMIC) PA design using Cadence AWR Microwave Office circuit desi... » read more

Faster Analog Design Closure With Early Parasitic Analysis Flow – Part 1

In part 1 of this series, Denis Goinard, Director of Engineering at Synopsys, discusses how Synopsys provides a unified workflow to accurately estimate, measure, extract and simulate parasitics by bringing signoff tools into the design process, enabling faster design convergence. Click here to play the video. Note: This is a Synopsys 'video white paper.' For more video white papers, click h... » read more

Constraints Ubiquity: Impact On Managing Design Closure?

By Mark Baker and Ravindra Aneja Maintaining completeness, correctness and consistency of design constraints is a challenge that is pervasive in the design flow. Multiple transformations, or touch points (as illustrated in the diagram below), exist during the design implementation stages. Additionally, there are parallel stages involving IP development and handoff resulting in SoC integration ... » read more