What Is The Definition Of Design For Context?

By Don Dingee - 17 Oct, 2022 - Comments: 0

EDA industry pundits and bloggers are latching onto a new term: design for context. So far, it has eluded a crisp yet complete definition. It's one of those ideas that if you ask ten people about it, you get ten different answers – some better than others. Ed Sperling wryly observed this in his recent panel discussions about the topic: "Even my questions are getting longer." When Keysight lis... » read more

Design For Context And Its Impact On EDA

By Frank Schirrmeister - 26 May, 2022 - Comments: 0

At the recent CEO panel, Ed Sperling used the term “Design for Context” as one of the key trends, identifying what others have referred to as “domain specific” or “workload specific.” The term struck a chord with me, as I see it in many customer meetings across various industry verticals in the context of a specific industry driving requirements for tools and IP. Undoubtedly, semico... » read more

CEO Outlook: Chip Industry 2022

By Ed Sperling - 02 May, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss broad industry changes and how that affects chip design with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a live audience... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: design for context

What Is The Definition Of Design For Context?

Design For Context And Its Impact On EDA

CEO Outlook: Chip Industry 2022