tag: DFT

Analog Fault Simulation Challenges And Solutions
By Mentor, a Siemens Business - 28 Sep, 2016 - Comments: 0

The test time for digital circuit blocks in ICs has greatly decreased in the last 20 years, thanks to scan-based design-for-test (DFT), automatic test pattern generation (ATPG) tools, and scan compression. These technologies have greatly reduced the number of test vectors applied by automatic test equipment (ATE) while maximizing the coverage of a wide range of defect types. But for analog c... » read more

Putting Design Back Into DFT
By Brian Bailey - 25 Aug, 2016 - Comments: 0

Test always has been a delicate balance between cost and quality, but there are several changes happening in the industry that might cause a significant alteration in strategy. Part one of this two part series about [getkc id="47" comment="Design for Test (DFT)"] looked at changes in areas such as automotive, where built in self-test is becoming a mandated part of the design process. This co... » read more

Gaps Emerge In Test Flows
By Ed Sperling - 04 Aug, 2016 - Comments: 0

Gaps are showing up in test flows as chipmakers add more analog content and push into more safety-critical applications, exposing more points at which designs need to be tested as well as weaknesses in current tools and methodologies. The cornerstone of the [getkc id="76" kc_name="IoT"], and connected devices such as self-driving cars, is a heavy reliance on [getkc id="187" kc_name="sensors"... » read more

Executive Insight: Jack Harding
By Ed Sperling - 03 Aug, 2016 - Comments: 0

[getperson id="11145" comment="Jack Harding"], president and CEO of [getentity id="22242" e_name="eSilicon"], sat down with Semiconductor Engineering to talk about consolidation, business relationships, what it will take to survive in the IoT age, and how to better optimize chips. What follows are excerpts of that conversation. SE: We’ve been looking at consolidation for a while and all th... » read more

Time To Pay The Piper
By Brian Bailey - 28 Jul, 2016 - Comments: 3

The Pied Piper of Hamelin is a German fable about a rat catcher who used his magic pipe to lure away rats. When he was not paid by the town, he used his pipe to lure away all of the town's children. I am not suggesting that exactly the same is true for the semiconductor industry and having not paid [getkc id="7" kc_name="EDA"], but I do not think they have paid enough and they will now have to ... » read more

New Drivers For Test
By Brian Bailey - 28 Jul, 2016 - Comments: 0

Mention Design for Test (DFT) and scan chains come to mind, but there is much more to it than that—and the rules of the game are changing. New application areas such as automotive may breathe new life into built-in self-test (BIST) solutions, which could also be used for manufacturing test. So could DFT as we know it be a thing of the past? Or will it continue to have a role to play? Te... » read more

Improve DFT Verification And Meet Time-To-Market Goals With Emulation
By Steve Dondershine - 30 Jun, 2016 - Comments: 0

What if all the DFT verification on your next big chip could be completed before tape-out? This “shift-left” of DFT verification would eliminate the need for shortcuts in verification and allow for more types of verification. The benefits of faster and earlier DFT verification include higher confidence in the “golden” RTL, eliminating DFT from the critical path of tape-out, and more pre... » read more

DAC Day Three: UVM, Machine Learning And DFT Come Together
By Brian Bailey - 08 Jun, 2016 - Comments: 0

The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex, unwieldy and difficult to learn. The third day of DAC gets started with breakfast with Accellera to discuss UVM and what we can expect to see in the next 5 years. The discussion was led by Tom Alsop, pri... » read more

The Week In Review: Design/IoT
By Jesse Allen - 09 Oct, 2015 - Comments: 0

Imec and Cadence completed the first tapeout of a 5nm test chip. Using a processor design, the companies taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning. Tools Synopsys folded in recent acquisition Atrenta's testabilit... » read more

Full AMS Design Flow For The IoT
By Mentor, a Siemens Business - 27 Aug, 2015 - Comments: 0

By Nicolas Williams and Jeff Miller The pressure for a new generation of (analog/mixed-signal) AMS design capabilities has been accelerated by the sudden demand for Internet of Things (IoT). These inexpensive devices are used in an expanding array of scenarios on the edge of the network — thus the demand for an AMS design environment that is affordable and easy to use, but powerful enough ... » read more

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