Top-Down Vs. Bottom-Up Chiplet Design

By Ann Mutschler - 26 Nov, 2024 - Comments: 0

Chiplets are gaining widespread attention across the semiconductor industry, but for this approach to really take off commercially it will require more standards, better modeling technologies and methodologies, and a hefty amount of investment and experimentation. The case for chiplets is well understood. They can speed up time to market with consistent results, at whatever process node work... » read more

AI/ML’s Role In Design And Test Expands

By Laura Peters - 06 Aug, 2024 - Comments: 1

The role of AI and ML in test keeps growing, providing significant time and money savings that often exceed initial expectations. But it doesn't work in all cases, sometimes even disrupting well-tested process flows with questionable return on investment. One of the big attractions of AI is its ability to apply analytics to large data sets that are otherwise limited by human capabilities. In... » read more

Five Digital Threads Unify And Simplify Electronic Systems Design And Manufacturing

By Matt Walsh - 25 Jan, 2024 - Comments: 0

By Matthew Walsh and Matt Bromley Digital transformation involves the integration of digital technologies and the reimagining of business processes to enhance operations, improve customer experiences, and drive innovation. Digital threads are a key component of this transformation, as they enable the seamless flow of data and information across various stages of a process, system, or organiz... » read more

Extending DTCO For Today’s Competitive IC Landscape

By Le Hong - 21 Dec, 2023 - Comments: 0

As semiconductor components continue to shrink, the challenges associated with design-for-manufacturing (DFM) and design-technology co-optimization (DTCO) increase. The complexity of the IC design and manufacturing process demands an extension of traditional DFM and DTCO techniques to overcome the systematic failures tied to complex design-process interactions. Designers need to accelerate d... » read more

Flexible Hybrid Electronics: Future Standards For Next-Gen 5G/mmWave Wearable and Conformal Applications

By Technical Paper Link - 15 Aug, 2023 - Comments: 0

A technical paper titled “Additively manufactured flexible on-package phased array antennas for 5G/mmWave wearable and conformal digital twin and massive MIMO applications” was published by researchers at Georgia Institute of Technology. Abstract: "This paper thoroughly investigates material characterization, reliability evaluation, fabrication, and assembly processes of additively manufa... » read more

Automotive MCUs: Digital Twin of the LBIST Functionality

By Technical Paper Link - 15 Feb, 2023 - Comments: 0

A new technical paper titled "A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin" was written by researchers at Infineon Technologies, University of Bremen, and DFKI GmbH. Abstract "LBIST has been proven to be an effective measure for reaching functional safety goals for automotive microcontrollers. Due to a large variety of recent innovative fea... » read more

Week In Review: Design, Low Power

By Marie C. Baca - 30 Sep, 2022 - Comments: 0

Tools and IP Renesas introduced a new microprocessor that enables artificial intelligence to process image data from multiple cameras. "One of the challenges for embedded systems developers who want to implement machine learning is to keep up with the latest AI models that are constantly evolving,” said Shigeki Kato, Vice President of Renesas' Enterprise Infrastructure Business Division. �... » read more

Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications

By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract: "The expansive globalization of the semiconductor supply chain has introduced numerous untrusted entities into different stages of a device’s lifecycle, enabling them to compromise its security. To make matters worse, the increasing complexity in the design as well as aggressive time-to-market requirements of the newer generation of integrated circuits can lead either designers t... » read more

Artificial Intelligence For Industrial Applications

By Dirk Mayer - 13 Feb, 2020 - Comments: 0

By Dirk Mayer and Olaf Enge-Rosenblatt Due to digitalization, modern machines and systems provide massive quantities of data, which form a significant basis for the optimization of production processes, operations and safety. These data sets, however, grow more and more complex, which renders the simple analysis methods typically used in the past often ineffective. This is one factor driv... » read more

Portable Stimulus And Digital Twins

By Brian Bailey - 25 Nov, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSp... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: digital twin