tag: DNN

Using Deep Learning ADC For Defect Classification For Automatic Defect Inspection
By Onto Innovation - 14 May, 2024 - Comments: 0

In traditional semiconductor packaging, manual defect review after automated optical inspection (AOI) is an arduous task for operators and engineers, involving review of both good and bad die. It is hard to avoid human errors when reviewing millions of defect images every day, and as a result, underkill or overkill of die can occur. Automatic defect classification (ADC) can reduce the number of... » read more

Improving ML-Based Device Modeling Using Variational Autoencoder Techniques
By Technical Paper Link - 27 Sep, 2023 - Comments: 0

A technical paper titled “Improving Semiconductor Device Modeling for Electronic Design Automation by Machine Learning Techniques” was published by researchers at Commonwealth Scientific and Industrial Research Organisation (CSIRO), Peking University, National University of Singapore, and University of New South Wales. Abstract: "The semiconductors industry benefits greatly from the integ... » read more

Photonic-Electronic SmartNIC With Fast and Energy-Efficient Photonic Computing Cores (MIT)
By Technical Paper Link - 19 Sep, 2023 - Comments: 0

A technical paper titled “Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference” was published by researchers at Massachusetts Institute of Technology (MIT). Abstract: "The massive growth of machine learning-based applications and the end of Moore's law have created a pressing need to redesign computing platforms. We propose Lightning, the first ... » read more

A Chiplet-Based FHE Accelerator Design Enabling Scalability And Higher Throughput
By Technical Paper Link - 07 Aug, 2023 - Comments: 0

A technical paper titled “REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption” was published by researchers at Graz University of Technology and Samsung Advanced Institute of Technology. Abstract: "Fully Homomorphic Encryption (FHE) has emerged as a promising technology for processing encrypted data without the need for decryption. Despite its potential, its... » read more

Leveraging Large Language Models (LLMs) To Perform SW-HW Co-Design
By Technical Paper Link - 28 Jun, 2023 - Comments: 0

A technical paper titled “On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators” was published by researchers at University of Notre Dame. Abstract: "Deep Neural Networks (DNNs) have demonstrated impressive performance across a wide range of tasks. However, deploying DNNs on edge devices poses significant challenges due to stringent power and com... » read more

Optimizing Projected PCM for Analog Computing-In-Memory Inferencing (IBM)
By Technical Paper Link - 22 May, 2023 - Comments: 0

A new technical paper titled "Optimization of Projected Phase Change Memory for Analog In-Memory Computing Inference" was published by researchers at IBM Research. "A systematic study of the electrical properties-including resistance values, memory window, resistance drift, read noise, and their impact on the accuracy of large neural networks of various types and with tens of millions of wei... » read more

Low-Power Heterogeneous Compute Cluster For TinyML DNN Inference And On-Chip Training
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training" was published by researchers at University of Bologna and ETH Zurich. Abstract "On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clus... » read more

Asynchronously Parallel Optimization Method For Sizing Analog Transistors Using Deep Neural Network Learning
By Technical Paper Link - 03 Mar, 2023 - Comments: 0

A new technical paper titled "APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning" was published by researchers at UT Austin and Analog Devices. Abstract "Analog circuit sizing is a high-cost process in terms of the manual effort invested and the computation time spent. With rapidly developing technology and high market demand, bringing automated s... » read more

Review of Tools & Techniques for DL Edge Inference
By Technical Paper Link - 16 Feb, 2023 - Comments: 0

A new technical paper titled "Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review" was published in "Proceedings of the IEEE" by researchers at University of Missouri and Texas Tech University. Abstract: Successful integration of deep neural networks (DNNs) or deep learning (DL) has resulted in breakthroughs in many areas. However, deploying thes... » read more

Multiexpert Adversarial Regularization For Robust And Data-Efficient Deep Supervised Learning
By Samsung - 16 Nov, 2022 - Comments: 0

Deep neural networks (DNNs) can achieve high accuracy when there is abundant training data that has the same distribution as the test data. In practical applications, data deficiency is often a concern. For classification tasks, the lack of enough labeled images in the training set often results in overfitting. Another issue is the mismatch between the training and the test domains, which resul... » read more

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