tag: DRAM

How Many Cores? (Part 2)
By Ed Sperling - 21 Mar, 2016 - Comments: 1

New chip architectures and new packaging options—including fan-outs and 2.5D—are changing basic design considerations for how many cores are needed, what they are used for, and how to solve some increasingly troublesome bottlenecks. As reported in part one, just adding more cores doesn't necessarily improve performance, and adding the wrong size or kinds of cores wastes power. That has s... » read more

Running Out Of Energy?
By Ann Mutschler - 16 Mar, 2016 - Comments: 1

The anticipated and growing energy requirements for future computing needs will hit a wall in the next 24 years if the current trajectory is correct. At that point, the world will not produce enough energy for all of the devices that are expected to be drawing power. A report issued by the Semiconductor Industry Association and Semiconductor Research Corp., bases its conclusions on system-le... » read more

New Memory Approaches And Issues
By Ed Sperling - 14 Mar, 2016 - Comments: 1

New memory types and approaches are being developed and tested as DRAM and Moore's Law both run out of steam, adding greatly to the confusion of what comes next and how that will affect chip designs. What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes. New architectures, such as [getkc id="202" kc_name="fan-outs"] and [getk... » read more

Optimizing DDR Memory Subsystem Efficiency
By Synopsys - 24 Feb, 2016 - Comments: 0

The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, t... » read more

What’s Next For DRAM?
By Mark LaPedus - 24 Feb, 2016 - Comments: 2

The DRAM business has always been challenging. Over the years, DRAM suppliers have experienced a number of boom and bust cycles in a competitive landscape. But now, the industry faces a cloudy, if not an uncertain, future. On one front, for example, [getkc id="93" kc_name="DRAM"] vendors face a downturn amid a capacity glut and falling product prices in 2016. But despite the business chal... » read more

1xnm DRAM Challenges
By Mark LaPedus - 18 Feb, 2016 - Comments: 3

At a recent event, Samsung presented a paper that described how the company plans to extend today’s planar DRAMs down to 20nm and beyond. This is an amazing feat. Until very recently, most engineers believed DRAMs would stop scaling at 20nm or so. Instead, Samsung is ramping up the world’s most advanced DRAMs—a line of 20nm parts—with plans to go even further. Micron and SK Hynix soo... » read more

Memory Lane: Far From A Leisurely Stroll
By Joanne Itow - 18 Feb, 2016 - Comments: 0

The only semiconductor market segment that has not been taken over by the foundries and still remains dominated by IDMs is the memory sector. The memory market is the last bastion for true IDM manufacturers, who must be savvy in the changing trends in end market applications, advanced technology development, and must still determine how much and when to invest in additional capacity. With on... » read more

An Insider’s Guide To Planar And 3D DRAM
By Mark LaPedus - 18 Feb, 2016 - Comments: 0

Semiconductor Engineering sat down to talk about planar DRAMs, 3D DRAMs, scaling and systems design with Charles Slayman, technical leader of engineering at network equipment giant Cisco Systems. What follows are excerpts of that conversation. SE: What types of DRAM do network equipment OEMs look at or buy these days? Slayman: When we look at DRAM, we look at it for networking applicatio... » read more

Will 3D-IC Work?
By Ed Sperling - 11 Feb, 2016 - Comments: 3

Advanced packaging is becoming real on every level, from fan-outs to advanced fan-outs, 2.5D, and 3D-ICs for memory. But just how far 3D and monolithic 3D will go isn't clear at this point. The reason is almost entirely due to heat. In a speech at SEMI's Integrated Strategy Symposium in January, Babek Sabi, Intel corporate VP and director of assembly and test technology development, warned t... » read more

Optimizing LPDDR4 Performance And Power With Multi-Channel Architectures
By Synopsys - 10 Feb, 2016 - Comments: 0

PDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper explains how LPDDR4 is different from all previous JEDEC... » read more

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