Memory And High-Speed Digital Design

By Ann Mutschler - 18 Oct, 2023 - Comments: 0

As DRAM gets faster, timing constraints, jitter, and signal integrity become harder to control. The real challenge is to understand what can go wrong early in the design process, and that becomes more complex with each new version of memory and higher signal speeds. Stephen Slater, product manager for EDA products at Keysight, talks about how simulation can be applied to these issues, what to t... » read more

CXL: The Future Of Memory Interconnect?

By Karen Heyman - 12 Oct, 2023 - Comments: 1

Momentum for sharing memory resources between processor cores is growing inside of data centers, where the explosion in data is driving the need to be able to scale memory up and down in a way that roughly mirrors how processors are used today. A year after the CXL Consortium and JEDEC signed a memorandum of understanding (MOU) to formalize collaboration between the two organizations, suppor... » read more

Week In Review: Manufacturing, Test

By Gregory Haley - 01 Sep, 2023 - Comments: 0

Bosch completed its acquisition of TSI Semiconductors to expand its SiC chips business, reports Reuters. In April, Bosch announced plans to invest $1.5 billion in the Roseville, California, foundry to convert TSI’s manufacturing facilities into state-of-the-art processes, with the first SiC chips due out in 2026. Bosch CEO Stefan Hartung said the full expansion "depends on the support of the... » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology

By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

A Practical DRAM-Based Multi-Level PIM Architecture For Data Analytics

By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics" was published by researchers at Korea Advanced Institute of Science & Technology (KAIST) and SK hynix Inc. Abstract: "Processing-in-memory (PIM) architecture is an inherent match for data analytics application, but we observe major challenges to address when accelerating it usi... » read more

RowPress: Read-Disturb Phenomenon In DDR4 DRAM Chips

By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "RowPress: Amplifying Read Disturbance in Modern DRAM Chips" was published by researchers at ETH Zürich. Abstract: "Memory isolation is critical for system reliability, security, and safety. Unfortunately, read disturbance can break memory isolation in modern DRAM chips. For example, RowHammer is a well-studied read-disturb phenomenon where repeatedly opening and clo... » read more

Week In Review: Semiconductor Manufacturing, Test

By Gregory Haley - 07 Jul, 2023 - Comments: 0

China retaliated against a U.S. embargo on advanced semiconductor equipment exports by restricting exports of gallium and germanium. Both metals are widely used in semiconductors and electric vehicles. Despite export controls for advanced chips and equipment imposed on Chinese foundries by the U.S. and its allies, TrendForce predicts China's 300mm market share likely will increase from 24% ... » read more

DRAM Translation Layer, Mechanism for Flexible Address Mapping and Data Migration Within CXL-Based Memory Devices

By Technical Paper Link - 06 Jul, 2023 - Comments: 0

A technical paper titled “DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory” was published by researchers at Seoul National University. Abstract: "Memory disaggregation is a promising solution to scale memory capacity and bandwidth shared by multiple server nodes in a flexible and cost-effective manner. DRAM power consumption, which is reported to be... » read more

Low Density Of LPDDR4x DRAM — The Best Choice For Edge AI

By Winbond - 05 Jul, 2023 - Comments: 0

Edge AI computes the data as close as possible to the physical system. The advantage is that the processing of data does not require a connected network. The computation of data happens near the edge of a network, where the data is being developed, instead of in a centralized data-processing center. One of the biggest benefits of edge AI is the ability to secure real-time results for time-sensi... » read more

Improving DRAM Device Performance Through Saddle Fin Process Optimization

By Taeyon (TY) Oh - 15 Jun, 2023 - Comments: 0

As DRAM technology nodes have scaled down, access transistor issues have been highlighted due to weak gate controllability. Saddle Fins with Buried Channel Array Transistors (BCAT) have subsequently been introduced to increase channel length, prevent short channel effects, and increase data retention times [1]. However, at technology nodes beyond 20nm, securing sufficient device performance (su... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: DRAM