Balancing On The Color Density Tightrope

By David Abercrombie - 19 Feb, 2015 - Comments: 0

Balancing on wobbly tightropes is something that chip designers get pretty good at. For instance, there is a fine balance between optimizing performance and minimizing leakage in a design layout. Dealing with the new requirements that multi-patterning (MP) introduces into a design flow creates many new tightropes to walk. I tiptoed out on one of the rarely talked about ones in my last article�... » read more

Rule Deck Comparison Doesn’t Have To Be Difficult

By Saunder Peng - 22 Jan, 2015 - Comments: 0

Foundry rule decks change all the time, as foundries uncover new manufacturing issues, or the process changes, or design criteria are tightened to improve runtime or stability. Sometimes new versions of a user’s design rule checking (DRC) tool are released, and the results from the DRC run differ from the previous version. Or perhaps a company wants to compare results between rule decks from ... » read more

Conflicting Needs For IoT Edge Designs

By Ed Sperling - 20 Nov, 2014 - Comments: 1

The mad rush has begun to hype the [getkc id="76" comment="Internet of Things"], but the path forward isn't quite as straightforward as the marketers would like it to be. ICs used at the edge of the IoT—the ones that gather information to be controlled by smart phones or tablets and transmitted to devices for processing and data analytics—need to be designed differently than the initial for... » read more

Design Rules Explode At New Nodes

By Ed Sperling - 17 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Design Rules Explode At New Nodes

By Ed Sperling - 16 Oct, 2014 - Comments: 0

The Route To Faster Physical Verification And Better Designs

By Jean-Marie Brunet - 18 Sep, 2014 - Comments: 0

By Nancy Nguyen & Jean-Marie Brunet As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to converge, power reduction for both IR and leakage becomes a big issue, and most importantly, how do we meet all of the ever-growing and more complex signoff d... » read more

Signoff Intensity On The Rise

By The SE Staff - 15 Aug, 2014 - Comments: 2

By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

A Guide To Advanced Process Design Kits

By Ernest Worthman - 14 Apr, 2014 - Comments: 1

The increasing complexity of design enablement has prompted manufacturers to optimize the design process. New tools and techniques, thanks to next-generation hardware and software, have provided a new platform for semiconductor and wafer design. Advanced PDKs are the solution and have been developed by foundries to optimize the design process and leverage and reuse intellectual property (IP) an... » read more

The Road Ahead For 2014: Tools

By Brian Bailey - 30 Jan, 2014 - Comments: 0

In the third and final part of this predictions series we see the natural conclusion of market shifts that are driving changes in semiconductors, and which in turn drive the tools and IP needed to create those systems. To be expected, the changes fall into a few areas: New tools, techniques and changes required for smaller geometries; A migration to higher-levels of abstraction and the... » read more

Fixing DP Errors: Colors Or Rings

By Ann Mutschler - 18 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: DRC

Balancing On The Color Density Tightrope

Rule Deck Comparison Doesn’t Have To Be Difficult

Conflicting Needs For IoT Edge Designs

Design Rules Explode At New Nodes

Design Rules Explode At New Nodes

The Route To Faster Physical Verification And Better Designs

Signoff Intensity On The Rise

A Guide To Advanced Process Design Kits

The Road Ahead For 2014: Tools

Fixing DP Errors: Colors Or Rings