tag: DVCon

Does Fast Simulation Help Debug Productivity?
By Brian Bailey - 09 Apr, 2015 - Comments: 0

It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

One-To-Many: Shifting Left, Adding Gears
By Brian Bailey - 12 Mar, 2015 - Comments: 3

[getperson id="11034" comment="Aart de Geus"], chairman and co-CEO of [getentity id="22035" e_name="Synopsys"], launched into high gear for his keynote talk at this year’s Design and Verification Conference (DVCon). The gathering attracted a record number of attendees, and it is estimated that about 350 people crammed into the room to listen to him talk about the shift left that is happening ... » read more

Biz Talk: Funding Strategies
By Brian Bailey - 11 Mar, 2015 - Comments: 0

Michel Courtoy, VP of marketing and business development at Kilopass, and a former member of the M&A group at Cadence , talks with Semiconductor Engineering about EDA startups, where to find funding, how long it takes to get established, and new exit strategies. [youtube vid=RMkuMiqb10M] » read more

Conferences, Education And The Press
By Brian Bailey - 25 Sep, 2014 - Comments: 1

The EDA industry once organized itself around conferences. The Design Automation Conference (DAC) marked the time of the year when new product announcements came out thick and fast, and it was difficult to keep up with the stream of press releases. Companies with nothing to announce were viewed as deficient. New products were demonstrated in secrecy in the back rooms of the suites at the confer... » read more

Blog Review: July 16
By Ed Sperling - 16 Jul, 2014 - Comments: 0

Mentor’s Scott Salzwedel describes a conversation that could very well happen in the future and it raises an interesting idea. As medical electronics proliferate, will emergency medical teams need to include out systems engineers? Cadence’s Brian Fuller has a summer engineering project that resembles the Bridge Over the River Kwai. He should win an Oscar for this one. Ansys’ Bill ... » read more

Blog Review: April 2
By Ed Sperling - 02 Apr, 2014 - Comments: 0

Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

Get Ready For DVCon Europe
By Accellera - 28 Mar, 2014 - Comments: 0

By Martin Barnasconi DVCon Europe, a new conference and exhibition around design and verification, will be held Oct. 14-15 in Munich, Germany. Call for abstracts for DVCon Europe is open through April 8. The obvious question is why DVCon Europe. DVCon and its predecessor conferences have been held successfully in the Silicon Valley for more than 20 years. The conference is extremely success... » read more

Big Shift In SoC Verification
By Ed Sperling - 17 Mar, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

More Pain In More Places
By Ed Sperling - 14 Mar, 2014 - Comments: 2

Pain is nothing new in to the semiconductor industry. In fact, the pain of getting complex designs completed on budget, and finding the bugs in those designs, has been responsible for decades of continuous growth in EDA, IP, test, packaging, and foundries. But going forward there is change afoot in every segment of the flow from architecture to design to layout to verification to manufacturi... » read more

Do We Need A “Glue” Engineer?
By Brian Fuller - 13 Mar, 2014 - Comments: 0

Design and verification are so complex today and fraught with market risk that it keeps managers awake and sweating at night. So much of design is carved up in IP blocks and subsystems, each with their own verification issues and methodologies. To manage the complexity the design is partitioned, and so too are the teams. But as software verification becomes more crucial to system-design succ... » read more

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