Application-Optimized Processors

By Ed Sperling - 29 Sep, 2023 - Comments: 0

Executing a neural network on top of an NPU requires an understanding of application requirements, such as latency and throughput, as well as the potential partitioning challenges. Sharad Chole, chief scientist and co-founder of Expedera, talks about fine-grained dependencies, why processing packets out of order can help optimize performance and power, and when to use voltage and frequency scal... » read more

Energy-Efficient Execution Scheme For Dynamic Neural Networks on Heterogeneous MPSoCs

By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCs" was published (preprint) by researchers at LAMIH/UMR CNRS, Universite Polytechnique Hauts-de-France and UC Irvine. Abstract "Heterogeneous MPSoCs comprise diverse processing units of varying compute capabilities. To date, the mapping strategies of neural networks (NNs) onto ... » read more

Screening For Silent Data Errors

By Anne Meixner - 10 Jan, 2023 - Comments: 0

Engineers are beginning to understand the causes of silent data errors (SDEs) and the data center failures they cause, both of which can be reduced by increasing test coverage and boosting inspection on critical layers. Silent data errors are so named because if engineers don’t look for them, then they don’t know they exist. Unlike other kinds of faulty behaviors, these errors also can c... » read more

Looking Inside Of Chips

By Ed Sperling - 10 Jan, 2023 - Comments: 0

Shai Cohen, co-founder and CEO of proteanTecs, sat down with Semiconductor Engineering to talk about how to boost reliability and add resiliency into chips and advanced packaging. What follows are excerpts of that conversation. SE: Several years ago, no one was thinking about on-chip monitoring. What's changed? Cohen: Today it is obvious that a solution is needed for optimizing performanc... » read more

Variability Becoming More Problematic, More Diverse

By Karen Heyman - 12 Dec, 2022 - Comments: 0

Process variability is becoming more problematic as transistor density increases, both in planar chips and in heterogeneous advanced packages. On the basis of sheer numbers, there are many more things that can wrong. “If you have a chip with 50 billion transistors, then there are 50 places where a one-in-a-billion event can happen,” said Rob Aitken, a Synopsys fellow. And if Intel’s... » read more

How Climate Change Affects Data Centers

By Marie C. Baca - 25 Aug, 2022 - Comments: 0

Data centers are hot, and they may get even hotter. As climate change impacts temperatures around the world, designers are changing the computing hubs that are tied to nearly every aspect of modern life to make them more efficient, more customized, and potentially more disaggregated. These shifts are taking on new urgency as the tech industry grapples with months of sweltering temperatures o... » read more

Effectiveness of a Reinforcement-Learning Based Dynamic Power Manager In a SW Framework

By Technical Paper Link - 13 Jul, 2022 - Comments: 0

New technical paper titled "Low-Overhead Reinforcement Learning-Based Power Management Using 2QoSM" from researchers at ETH Zurich and Georgia Tech. Abstract "With the computational systems of even embedded devices becoming ever more powerful, there is a need for more effective and pro-active methods of dynamic power management. The work presented in this paper demonstrates the effectiven... » read more

Hertzbleed: A New Family of Side-Channel Attacks–Root Case: Dynamic Frequency Scaling

By Technical Paper Link - 01 Jul, 2022 - Comments: 0

New research paper titled "Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86" from researchers at UT Austin, University of Illinois Urbana-Champaign (UIUC) and University of Washington can be found here. (preprint). This paper will be presented at the 31st USENIX Security Symposium (Boston, 10–12 August 2022). Summary explanation of the Hertzbleed ... » read more

Effect of Different Frequency Scaling Levels on Memory in Regard to Total Power Consumption in Mobile MPSoC

By Technical Paper Link - 06 Jun, 2022 - Comments: 0

New technical paper titled "CPU-GPU-Memory DVFS for Power-Efficient MPSoC in Mobile Cyber Physical Systems" from researchers at University of Essex, Nosh Technologies, and University of Southampton. Abstract "Most modern mobile cyber-physical systems such as smartphones come equipped with multi-processor systems-on-chip (MPSoCs) with variant computing capacity both to cater to performance r... » read more

Analytical Energy Model Parametrized by Workload, Clock Frequency and Number of Active Cores for Share-Memory High-Performance Computing Applications

By Technical Paper Link - 04 Apr, 2022 - Comments: 0

New academic paper from University of Mons (Belgium) and Universidade Federal do Rio Grande do Norte (Brazil). Abstract "Energy consumption is crucial in high-performance computing (HPC), especially to enable the next exascale generation. Hence, modern systems implement various hardware and software features for power management. Nonetheless, due to numerous different implementations, we ca... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?