tag: DVFS

System-Level Power Modeling Takes Root
By Ann Mutschler - 10 May, 2018 - Comments: 0

Power, heat, and their combined effects on aging and reliability, are becoming increasingly critical variables in the design of chips that will be used across a variety of new and existing markets. As more processing moves to edge, where sensors are generating a tsunami of data, there are a number of factors that need to be considered in designs. On one side, power budgets need to reflect th... » read more

What Happened To UPF?
By Brian Bailey - 16 Apr, 2018 - Comments: 1

Two years ago there was a lot of excitement, both within the industry and the standards communities, about rapid advancements that were being made around low-power design, languages and methodologies. Since then, everything has gone quiet. What happened? At the time, it was reported that the [gettech id="31043" comment="IEEE 1801"] committee was the largest active committee within the IEEE. ... » read more

Thermal Issues And Modern SoCs: How Hot Is Hot?
By Ramsay Allen - 16 Mar, 2018 - Comments: 0

A Q&A with Moortec CTO Oliver King. What are the thermal issues of modern SoCs? Gate density has been increasing with each node and that pushes up power per unit area, and I think that has become an even bigger issue with FinFET processes where the channels are more thermally isolated than the planar processes before them. In the last few planar nodes, leakage was an issue which led ... » read more

IP And Power
By Brian Bailey - 08 Mar, 2018 - Comments: 0

[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

New Thermal Issues Emerge
By Ann Mutschler - 12 Feb, 2018 - Comments: 0

Thermal monitoring is becoming more critical as gate density continues to increase at each new node and as chips are developed for safety critical markets such as automotive. This may sound counterintuitive because the whole point of device scaling is to increase gate density. But at 10/7 and 7/5nm, static current leakage is becoming a bigger issue, raising questions about how long [getkc id... » read more

The Implementation Of Embedded PVT Monitoring Subsystems In Today’s Cutting Edge Technologies
By Moortec - 13 Dec, 2017 - Comments: 0

This new whitepaper from Moortec takes a comprehensive look at the Implementation of Embedded PVT Monitoring Subsystems in Today’s Cutting Edge Technologies and how this can benefit today’s advanced node semiconductor design engineers by improving the performance and reliability of SoC designs. With advances in CMOS technology, and the scaling of transistor channel lengths to nanometer (nm)... » read more

The Importance Of Embedded In-Chip Monitoring In Advanced Node CMOS Technology
By Oliver King - 09 Nov, 2017 - Comments: 0

By Oliver King & Ramsay Allen With advances in CMOS technology and the scaling of transistor channel lengths to nanometer (nm) dimensions, the density of digital circuits per unit area of silicon has increased as has the process variability of devices manufactured. The increase in digital logic (or gate) density, which equates to an increase in power density, is a major contributor to... » read more

Power Challenges At 10nm And Below
By Ann Mutschler - 11 May, 2017 - Comments: 1

Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Closing The Loop On Power Optimization
By Brian Bailey - 11 May, 2017 - Comments: 2

[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

Power Impacting Cost Of Chips
By Brian Bailey - 15 Mar, 2017 - Comments: 0

The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

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