tag: dynamic voltage drop

Is Your Voltage Drop Flow Obsolete?
By Marc Swinnen - 13 Nov, 2023 - Comments: 0

Voltage drop at advanced nodes is a deadly serious problem that has become unmanageable with the methodologies used by most chip designers today. This article will cover the reasons why power integrity has risen to a top-of-mind concern and why it has become almost impossible for today’s EDA tools to measure and fix it. We will then look at some radical methodology rethinking that is needed t... » read more

Automated Late Stage Timing-Aware Dynamic Voltage Drop ECO
By Manoj Chacko - 09 Jan, 2023 - Comments: 0

One of the never-ending frustrations for electrical engineers is having to deal with counterproductive real-world effects that they wish would just go away. Examples include switch bounce, metastability, and contact resistance. For IC designers, dynamic voltage drop (DVD), also known as IR drop, is one of those unfortunate facts of the profession. There’s no way to avoid it; every trace and w... » read more

Always-On, Ultra-Low-Power Design Gains Traction
By Ann Mutschler - 14 Apr, 2022 - Comments: 0

A surge of electronic devices powered by batteries, combined with ever-increasing demand for more features, intelligence, and performance, is putting a premium on chip designs that require much lower power. This is especially true for always-on circuits, which are being added into AR/VR, automotive applications with over-the-air updates, security cameras, drones, and robotics. Also known as ... » read more

Clocks Getting Skewed Up
By Brian Bailey - 30 Mar, 2022 - Comments: 0

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it's fraught with the most problems at the physical level. To some, the clock is the AC power supply of the chip. To others, it is an analog network almost beyond analysis. Ironically, there are no languages to describe clocking, few tools t... » read more

Overcoming The Growing Challenge Of Dynamic IR-Drop
By PV Srinivas - 24 Mar, 2022 - Comments: 0

IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer learns. But the challenges related to IR-drop (sometimes called voltage drop) have increased considerably in recent years, especially the dynamic IR-drop in the power/ground grid as circuits swi... » read more

Understanding Voltage Drop Mechanics
By Ann Mutschler - 13 Apr, 2017 - Comments: 0

As a fundamental concept of electronic design, voltage drop ranks highly as one to understand well. I particularly appreciate when industry folks come up with creative ways to get the point across. Jerry Zhao, a product management director at Cadence and I were discussing how to best manage dynamic and static voltage drop, but I first asked him to explain the difference between the two. I p... » read more

Managing Voltage Drop At 10/7nm
By Ann Mutschler - 13 Apr, 2017 - Comments: 0

Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

Dynamic Peak Power As A Proxy For DVD? Really?
By Tobias Bjerregaard - 08 Dec, 2016 - Comments: 0

Dynamic-voltage-drop (DVD) concerns have grown substantially at the 10nm and 7nm silicon process nodes. DVD refers to the transient voltage drop that a local power grid on a chip might experience if there is a rapid change in current. That drop can act like a “stall,” hurting performance until the grid recovers. Beefing up the power grid metal might seem to be the obvious fix, but, at th... » read more

Hitting The Power Integrity Wall At 10nm
By Tobias Bjerregaard - 08 Sep, 2016 - Comments: 0

At 10nm and beyond, the breakdown of some historic trends tied to Moore's Law is making it harder to fully harvest the benefits of scaling semiconductor technologies. Underlying the power, performance and area benefits of scaling are technological challenges that must be solved in order to make the semiconductor products a profitable business. Power-related challenges are among the most pres... » read more

Power Integrity Optimization Cuts RF Substrate Noise
By Tobias Bjerregaard - 14 Apr, 2016 - Comments: 0

Our main focus is on dynamic voltage drop at 16-14-10nm and beyond, but the rise of the Internet of Things (IoT) prompted me to share some silicon measurement results that are relevant to the RF design community. Normally, power integrity (PI) is looked at in the time domain, but in this work we looked at it from a frequency spectrum perspective. Silicon measurements prove how shaping the dynam... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy