Blog Review: Sept. 23

Arm's Matthew Mattina introduces a method to reduce the cost of neural network inference by combining both low-precision representation and the complexity-reducing Winograd transform while maintaining accuracy. Cadence's Paul McLellan checks out some of the biggest machine learning systems from Nvidia, Google, and Cerebras that were presented at the recent Hot Chips. Mentor's Robin Bornof... » read more

Plugging Gaps In Advanced Packaging

The growing difficulty of cramming more features into an SoC is driving the entire chip industry to consider new packaging options, whether that is a more complex, integrated SoC or some type of advanced packaging that includes multiple chips. Most of the work done in this area so far has been highly customized. But as advanced packaging heads into the mainstream, gaps are beginning to appea... » read more

Designing SoC Power Networks

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

SoC Power Grid Challenges

The consumption of power and dissipation of heat within large SoCs has received a lot of attention recently, but that is only part of the issue. Power also has to be reliably delivered onto and around the system. This is becoming increasingly difficult, and new nodes are adding to the list of challenges. "If we were building chips where there was only a single Vdd and Vss then it is not that... » read more

Stacked Die, Phase Two

The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

Is The Stacked Die Ecosystem Stagnating?

It is now widely agreed that not much has been happening in terms of adoption for 2.5D interposer and 3D ICs. “It seems like everyone is still at the starting line waiting for the race to begin," said Javier DeLaCruz, senior director of engineering of [getentity id="22242" e_name="eSilicon"]. "Interposer assembly and IP availability for effectively using the [getkc id="82" comment="2.5D IC... » read more

2.5D Timetable Coming Into Focus

After years of empty promises, the timetable for [getkc id="82" kc_name="2.5D"] is coming into better focus. Large and midsize chipmakers are behind it, real silicon is being developed, and contracts are being signed. That doesn't mean all of the pieces are in place or that market uptake is at the neck of the hockey stick. And it certainly doesn't mean the semiconductor industry is going to ... » read more

Experts at the Table: Stacking the Deck

By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of Eda2Asic Consulting. ... » read more

Experts At The Table: Stacking The Deck

By Ann Steffora Mutschler There is no doubt 3D stacking brings challenges not only from the design perspective, but also on the tool side. EDA vendors have been working for more than a few years to ready tools for stacked-die designs. How smooth the transition is, however, is a big question mark. Because the approach is new, not all the challenges are fully understood yet. And while most ED... » read more