Experts At The Table: Stacking The Deck

First of three parts: Planning for success in 3D ICs isn’t so easy, particularly when power and thermal issues are factored in. Tools have been created, but are largely untested and may need modification.


By Ann Steffora Mutschler
There is no doubt 3D stacking brings challenges not only from the design perspective, but also on the tool side. EDA vendors have been working for more than a few years to ready tools for stacked-die designs.

How smooth the transition is, however, is a big question mark. Because the approach is new, not all the challenges are fully understood yet. And while most EDA vendors believe the tools are in good shape, questions remain.

“In respect to challenges to 3D from an EDA tool perspective, it is very important [to make] sure that the custom, the digital and the package are very well integrated because 3D is about that heterogeneous system,” said Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence Design Systems. Therefore, bringing all the components together seamlessly is important as the foundation. That’s challenging too, she pointed out. “It’s not easy to make sure that you’re integrating all these platforms.”

She’s not alone in this assessment. Carey Robertson, product marketing director at Mentor Graphics, said he is watching to see if the industry will realize the 3D appeal in as non-disruptive a way as possible.

“Designers are counting on EDA tools to provide that,” Robertson said. “There are going to be some disruptions and the question is how much? We don’t see a lot of customers yet designing with 3D in mind. They are looking at it as 3D will be some cost savings over yield savings to, ‘Yes, I’m designing systems today and 3D is just a new way to do systems. I’ll put my analog on 65nm and my digital on 20nm, slap it all together and it’ll be fantastic.’ For customers who are more forward looking, they are thinking, ‘I’ll take advantage of 3D for Wide I/O applications and I will have a performance benefit.’”

Chipmakers are still thinking about how to best take advantage of 3D technology, but all are counting on the tool community to provide an infrastructure that allows engineering teams to make the decisions that they want to make in a way that still feels like a 2D world to them, he said. “We’re going to try to get there but there are certainly some hiccups: power and thermal are certainly a big concern.”

Karthik Chandrasekar, member of technical staff in IC Design at Altera, agreed. “I’ve been hearing talk of 3D for the past 10 years, right from the time I was in grad school. I still see the biggest challenge as being power and thermal issues because we have so much power density per unit area. How exactly are we going to cool this technology without resorting to anything exotic, and how manufacturable is it?”

He explained that considering the kinds of products Altera is building today, they are not conceived to be 3D from the ground up in this sense that they are not actually partitioned architecturally at a very fine-grain level. Some of the key challenges for Altera include ensuring interoperability between different CAD tools when the dies are assembled. That requires the engineering team to follow known good practices for integration, making sure to verify the connectivity. Chandrasekar recommends verifying the use of DRC LVS in a standardized method in order to avoid fundamental incompatibilities.

At the end of the day, some of the existing EDA tools can scale to what Altera’s engineers need them to do with minor extensions and known good practices followed, he said. But there are caveats. “If you look down to the future—let’s say three to five years down the line—then we are facing a giant explosion in products. You could have a lot of partitioning at a very fine-grain level. There is a need for standards and how you can interface between different CAD tools.”

Cadence’s Bansal agreed. In order to make the entire flow efficient, interoperability that is made possible through standards will be a requirement. “Let’s be practical, the chips are going to come from different places and they probably will be in different implementation systems,” she said. Not necessarily everybody is going to use all Cadence tools or all Synopsys tools or all Mentor tools. Just as now, it will be a combination. “In a realistic scenario we have to enable a system that is interoperable not only within one EDA vendor. It’s not about just digital, custom and package. It’s actually between the vendors, between the foundries. That standardization is also something as a forward-looking thing that we have to start thinking about.”

Herb Reiter, president of Eda2Asic Consulting said there are enough opportunities for a big transition with 3D design. “We have 100,000 guys who make a living designing systems and ICs and 3D IC technology shouldn’t be called 3D IC because it’s really not an integrated circuit anymore—it’s a system technology. I’ve given a lot of presentations in the last four years for the GSA and what I enjoyed most was when in the last row a system designers stood up and said, ‘Hold on a second, you are telling me that I can design my next system at half the power, twice the speed and lower cost? When can I have this?’ The demand from the system side is enormous for this technology. IC designers see it as an extra challenge and we need to of course work through the IC designers into the system space. At the same time we should look at this ecosystem and … we have to build more building blocks because as systems are larger entities you cannot do them on the low level anymore. You cannot design everything from scratch. You need to have system blocks. We need standards.”

To this end, Reiter has been working with Sematech 3D Enablement Center, where standards are a big topic for the participants including Intel, IBM, Samsung, GlobalFoundries, TSMC and others sitting together to discuss how to make a system that’s working together and also cost effective.

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