Accelerate Custom Layout Using Custom Compiler’s User-Defined Device (UDD)

By Synopsys - 24 Mar, 2021 - Comments: 0

In this 7th video of the series, Kai Wang, Director of Engineering at Synopsys, discusses in-design electrical analysis, and why it is critical to use signoff engines to check and fix resistance, capacitance and electromigration issues during layout. Click here to access this video whitepaper. » read more

Electro-Thermal Signoff For Next Gen 3DICs

By Ansys - 09 Sep, 2020 - Comments: 0

Multi-die designs, 2.5D and 3D, have been rising in popularity as they offer tremendously increased levels of integration, a smaller footprint, performance gains and more. While they are attractive for many applications, they also create design bottlenecks in the areas of thermal management and power delivery. For 3DICs, in addition to the complex SoC/PCB interactions seen in their 2D counterpa... » read more

Heat Problems Grow With FinFETs, 3D-ICs

By Ann Mutschler - 13 Feb, 2014 - Comments: 2

From high-end consumer devices to rack-mounted arrays inside of data centers, thermal issues are becoming more serious—and getting much more attention. Driving this shift is the move from single chips to 3D ICs, whether they are interposer-based or stacked die. It’s a well-understood challenge: Die stacking can cause thermal issues because of the lack of a readily accessible thermal diss... » read more

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tag: electrical design signoff

Accelerate Custom Layout Using Custom Compiler’s User-Defined Device (UDD)

Electro-Thermal Signoff For Next Gen 3DICs

Heat Problems Grow With FinFETs, 3D-ICs