Reflections On 2015


It is easy to make predictions, but few people can make them with any degree of accuracy. Most of the time, those predictions are forgotten by the end of the year and there is no one to do a tally of who holds more credibility for next year. Not so with SemiEngineering. We like to hold people's feet to the fire, but while the Pants-On-Fire meter may be applicable to politicians, we like to thin... » read more

Who’s Profiting From Complexity


Tool vendors' profits increasingly are coming from segments that performed relatively poorly in the past, reflecting both a rise in complexity in designing chips and big improvements in the tools themselves. The impacts of power, memory congestion, advanced-node effects such as process variation, [getkc id="160" kc_name="electromigration"] and RC delay in [getkc id="36" kc_name="interconnect... » read more

The Human Bottleneck


The history of semiconductor technology can be neatly summed up as a race to eliminate the next bottleneck. This is often done one process node at a time across an increasingly complex ecosystem. And it usually involves a high level of frustration, because the biggest problems stem from areas where engineering teams generally can't do anything about them. Concerns over the years have ranged ... » read more

2016 And Beyond


Greek mythology and Roman history are replete with soothsayers, some of whom got it right and others wrong. Cassandra was cursed that her predictions wouldn’t be believed, even though she predicted the Trojan horse. Caesar’s soothsayer predicted the demise of Julius Caesar during the Ides of March, which Caesar himself was skeptical about, but indeed he was murdered before the Ides passed. ... » read more

Hardware Models For Software


Shift left, while a relatively new term, has become important in all parts of the SoC design flow, but its impacts are wide ranging and many still ill defined. It basically means that tasks have to be started earlier than in the past because more accuracy is required from tasks that are further down in the flow in order to make better predictions. It also implies that more steps are performed c... » read more

Innovating Virtualization In Emulation


Last week we officially introduced our next-generation emulator. We used the words “datacenter” and “virtualization” a lot, and it is worthwhile to underline the significance of what just happened in emulation. The new concepts are just as key to emulation as was the invention of virtual memory and memory management units to processors and software development. The concept of virtual... » read more

One Flow To Rule Them All


The new mantra of shift left within EDA is nothing new and first made an appearance more than a decade ago. At that time there was a very large divide between logic synthesis and place and route. As wire delays became more important, timing closure became increasingly difficult with a logic synthesis flow that did not take that into account. The tools subsequently became tied much closer togeth... » read more

The Cloud, The IoE, And You


If you’re anywhere in the high-tech biz, the two terms that are rocking your world are the Internet of Everything and the Cloud. Whether you are on the inside track of these, or on the sidelines, they are going to be two of the most disruptive technologies of the 21st century. The cloud is already here and gaining momentum. Some people will argue that the cloud has been here since the ince... » read more

SoC Verification For The Internet of Things


Larger, more complex designs with more software and tighter power budgets require new verification solutions that target the associated technological challenges. This paper explores why traditional digital simulation and hardware prototypes fall short when it comes to verifying IoT and network designs, why using emulation is critical for a total verification solution, and why traditional in-cir... » read more

Hybrid Emulation Gets More Hybrid


Rising chip complexity is creating a booming emulation business, as chipmakers working at advanced nodes turn to bigger iron to get chips out the door on time. What started as a "shift lift"—doing more things earlier in the design cycle—is evolving into a more complex mix of hardware-accelerated verification for both hardware and software. There are even some new forays into power explor... » read more

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