Design By Architect Or Committee?

By Brian Bailey - 26 Mar, 2015 - Comments: 5

Everything we do is based on a language. It doesn’t matter if we are talking about design, verification, specification, software or mask data. They all provide a way to communicate intent, and then there are engines that work on the intent to produce something else that is desirable, also based on a language. Over time, the EDA industry has built up a hierarchy of languages from the most deta... » read more

Veloce System-Level Power Analysis And Verification

By Mentor, a Siemens Business - 11 Mar, 2015 - Comments: 0

Power analysis and verification need to move to the system level, improving upon and extending the capabilities and scope of RTL and gate-level techniques. The performance, capacity, and flexibility of emulation platforms make them the ideal technology for system-level power analysis and verification. Veloce delivers unprecedented power verification and analysis capabilities. This paper shares ... » read more

Getting The Right Return On Invested Power Consumption

By Frank Schirrmeister - 26 Feb, 2015 - Comments: 0

Three weeks ago, I participated in a panel on low power and modeling at the system level. It took place at DesignCon 2015 in Santa Clara, together with representatives from AMD, Avago, and Qualcomm. Interestingly enough, it gave me the opportunity to set some of the myths and dis-information about power consumption in emulation straight, but more on that later. The panel was moderated by Steve ... » read more

Who Pays For EDA Shift Left?

By Brian Bailey - 12 Feb, 2015 - Comments: 0

While working on the predictions articles for 2015 (markets, design, semiconductors, tools and flows), a number of companies talked about the great shift left that is happening in the industry. What was surprising was the number of companies that mentioned it, and in very different ways. It is clear that shift left does not mean the same thing to all people. While they all see it addressing ... » read more

Emulation Uses Increase

By Ed Sperling - 12 Feb, 2015 - Comments: 0

For more than two decades, [getkc id="30" comment="emulation"] was a technology in search of a market. While on paper it has always made sense to speed up simulation, using hardware acceleration was so pricey that few companies could justify the cost. Fast-forward to today and emulation is a major contributor to the bottom line at all of the Big Three [getkc id="7" kc_name="EDA"] companies. ... » read more

Optimizing Emulator Utilization

By Mentor, a Siemens Business - 11 Feb, 2015 - Comments: 0

Russ Klein describes how Codelink, a Mentor Graphics trace-based debug tool, gives software developers a traditional software debug view from a unique processor trace, enabling them to increase emulator utilization and enjoy a more productive debug experience. Codelink allows for software debug earlier in the design cycle, as it makes it possible to use the emulator without having debug circuit... » read more

Tools And Flows In 2015

By Brian Bailey - 29 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

The Danger of Using Patents

By Brian Bailey - 23 Jan, 2015 - Comments: 2

As I have written about recently, [getkc id="30" kc_name="emulation"] is a hot topic for EDA and the number and length of lawsuits related to the technology is almost overwhelming. The latest phase has just concluded with a summary judgment against [getentity id="22035" e_name="Synopsys"] on Jan. 20. It all started in late 2012 when Synopsys, which had just acquired [getentity id="22738" e_nam... » read more

Unraveling Power Methodologies

By Brian Bailey - 15 Jan, 2015 - Comments: 0

When working on articles, the editors at Semiconductor Engineering sometimes hear things that make them stand back and question what seems to be an industry truth. One such statement happened last month while researching a different article. The statement was: Most designs are not top-down, but in fact bottom-up when it comes to power management. The most used methodology today is that the RTL... » read more

Virtual Prototyping Takes Off

By Ed Sperling - 03 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss [getkc id="104" kc_name="virtual prototyping"] with Barry Spotts, senior core competency FAE for fabric and tools at [getentity id="22186" comment="ARM"]; Vasan Karighattam, senior director of architecture for SoC and SSW engineering at [getentity id="22664" e_name="Open-Silicon"]; Tom De Schutter, senior product marketing manager for Virtualizer So... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: emulation