tag: emulation

Rethinking Manufacturing Models
By Ed Sperling - 23 Jul, 2015 - Comments: 0

The perennial uncertainty surrounding EUV lithography and complications stemming from the most advanced nodes are creating a domino effect across the semiconductor industry. Rather than stalling the market, though, which is what happened with the transition to 20nm, vendors now are accelerating their product rollouts and adjusting business plans to capitalize on those delays. That includes m... » read more

UVM: What’s Stopping You?
By Doug Amos - 02 Jul, 2015 - Comments: 0

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

Executive Insight: Wally Rhines
By Ed Sperling - 01 Jul, 2015 - Comments: 0

Wally Rhines, chairman and CEO of Mentor Graphics, sat down with Semiconductor Engineering to talk about what's changing across a wide swath of the industry, where the new opportunities will be, when security will become a real opportunity for EDA, and why Moore's Law will die but progress will continue forever. SE: Looking back over the past year, what's changed and where are the possible r... » read more

Wrong Verification Revolution Offered
By Brian Bailey - 25 Jun, 2015 - Comments: 0

SoC design traditionally has been an ad-hoc process, with implementation occurring at the register transfer level. This is where verification starts, and after the blocks have been verified, it becomes an iterative process of integration and verification that continues until the complete system has been assembled. But today, this methodology has at least two major problems, which were addres... » read more

Towards A Metric To Measure Verification Computing Efficiency
By Frank Schirrmeister - 25 Jun, 2015 - Comments: 1

Thinking back about DAC 2015 in San Francisco earlier this month, I am happy that at least some of my predictions came true—there was clearly a trend towards making verification smarter. However, one thing struck me while hearing all the discussions on connecting engines is what Jim Hogan called the continuum of verification engines (COVE)—and what we at Cadence call the system development ... » read more

Power Verification Now Required
By Ann Mutschler - 17 Jun, 2015 - Comments: 0

Today’s verification tasks may seem daunting — and much of it is — but all of it is absolutely necessary to make sure chips operate properly with a larger system. Throw power into the mix and the challenges mount. The good news is that there is no shortage of tools and methodologies to help with these tasks. The bad news is that even the best tools won’t make the challenges disappear... » read more

SoC Integration Headaches Grow
By Ed Sperling - 16 Jun, 2015 - Comments: 0

As the number of IP blocks grows, so do the headaches of integrating the various pieces and making sure they perform as planned within a prescribed power envelope. This is easier said than done, particularly at the most advanced process nodes. There are more blocks, more power domains, more states and use-model dependencies, and there is much more contention for memories. There are physical ... » read more

The Old Two-Step Just Doesn’t Have That Swing
By Lauro Rizzatti - 16 Jun, 2015 - Comments: 0

Power analysis has quickly become equally as important as functional verification for today's power-hungry SoCs. Yet, until now, it was not possible to fully analyze dynamic power in very large SoCs running embedded software. That day has finally arrived with new emulation platform software that overcomes the intrinsic shortcomings of the current two-step power estimation tools. The current ... » read more

Mentor, Cadence Join Forces
By Ed Sperling - 15 Jun, 2015 - Comments: 0

Mentor Graphics and Cadence have agreed to create a single binary interface for their respective simulation and emulation platforms, allowing debug tools from one vendor to run on the other's platforms. The two have invited [getentity id="22035" e_name="Synopsys"] to join their initiative, as well. So far, there is no decision. The move proposes a single API for both [getentity id="22032"... » read more

Power Usage Shift Leads To Methodology Shift
By Mentor, a Siemens Business - 15 Jun, 2015 - Comments: 0

Veloce offers a unique and customized flow for SoC power exploration and analysis. Veloce Power Application is enabling a methodology shift in the way power measurements are done to address the new requirements due to usage shift. Chip designers do not need to rely on functional test benches and extrapolation techniques to come up with power number. The new flow enables booting OS, running live... » read more

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