tag: emulation

Abstraction: Necessary But Evil
By Brian Bailey - 14 Oct, 2015 - Comments: 1

Abstraction allows aspects of a design to be described in an executable form much earlier in the flow. But some abstractions are breaking down, and an increasing amount of lower-level information has to be brought upstream in order to provide estimates that are close enough to reality so informed decisions can be made. The value of abstractions in design cannot be overstated. High levels of ... » read more

A Word About FPGA-Based Prototyping
By Tom De Schutter - 24 Sep, 2015 - Comments: 0

With software now driving the main capabilities of embedded devices, prototyping has taken the spotlight in SoC design. This is turning a once-hardware-centric electronics supply chain upside down. To cope with this new reality, companies are embracing both virtual and physical prototyping technologies. Physical prototyping, also known as FPGA-based prototyping, is an important piece of an e... » read more

Property Synthesis Throughout The Design Flow For Application In Formal Verification, Simulation, And Emulation
By Cadence - 23 Sep, 2015 - Comments: 0

This white paper describes the JasperGold Property Synthesis Apps, members of a family of interoperable, application-specific formal verification solutions that addresses verification challenges throughout the design flow. The Apps synthesize both behavioral and structural properties — also known as assertions — for use in formal verification, simulation and emulation. They significantly in... » read more

SoC Verification Made Easy With Aldec HES-DVM
By Aldec - 23 Sep, 2015 - Comments: 0

As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, therefore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This document... » read more

Power Estimation: Early Warning System Or False Alarm?
By Brian Bailey - 10 Sep, 2015 - Comments: 0

Semiconductor Engineering sat down with a large panel of experts to discuss the state of power estimation and to find out if the current levels of accuracy are sufficient to being able to make informed decisions. Panelists included: Leah Schuth, director of technical marketing in the physical design group at [getentity id="22186" comment="ARM"]; Vic Kulkarni, senior vice president and general m... » read more

Tech Talk: Power Emulation
By Ed Sperling - 10 Sep, 2015 - Comments: 0

Jean-Marie Brunet, marketing director for Mentor Graphics' Emulation Division, talks about why hardware-assisted verification is now required for power and where it works best. [youtube vid=Mb63cbjbZ_I] » read more

How To Speed Up Networking Design Verification
By Lauro Rizzatti - 10 Sep, 2015 - Comments: 0

The enormous growth of the Internet of things (IoT) has an enormous impact on network providers. After all, without the underlying network infrastructure, there would be no IoT. One consequence has been a significant increase in the number of Ethernet ports on networking devices. Today, Ethernet switches and routers reach 256 ports (by year’s end that number will increase to 1024 ports), a... » read more

Accelerating Networking Products To Market Using Ethernet VirtuaLAB
By Mentor, a Siemens Business - 09 Sep, 2015 - Comments: 0

A larger number of ports, expanding throughput, decreasing latency and overall improvement in security and ease-of-use are making today’s network switches and routers among the largest IC designs ever developed, reaching beyond a half billion gates. Verification of such complex IC designs, before silicon availability, is a daunting task. A fast, accurate, easy-to-use solution, VirtuaLAB bring... » read more

Executive Insight: Sanjiv Kaul
By Ed Sperling - 02 Sep, 2015 - Comments: 0

Sanjiv Kaul, president and CEO of [getentity id="22016" e_name="Calypto"], sat down with Semiconductor Engineering to talk about dynamic power concerns in finFETs, where software fits in, and why high-level synthesis is now a competitive requirement at advanced nodes. What follows are excerpts of that conversation. SE: What's the biggest problem the semiconductor industry is facing right no... » read more

From Simulation To Emulation
By Mentor, a Siemens Business - 12 Aug, 2015 - Comments: 0

This paper introduces an acceleration-ready UVM framework and explains why it is needed, how to create it, and what its benefits are. By following the principles presented here, users will be able to write block-level UVM environments that can be reused directly in emulation. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy