What’s Ahead For System-Level Design


By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must be integrated, among other things, the challenges just keep mounting. Depending on what market segment the SoC will be designed into has a huge impact, as well. “It is impossible to ove... » read more

Addressing Today’s Complex Clock Modeling Issues With Veloce Emulation Technology


Earlier designs were smaller, less complex, and had simpler clocking. A few years back, verification was much easier and clock modeling was not such a big concern. With the drastic increase in the use of System-on-Chip (SoC), designs today are becoming extremely complex with an increasing number of peripherals/external interfaces to consider, requiring a higher numbers of asynchronous clocks. ... » read more

On Design Productivity And Cost of Ownership …


By Frank Schirrmeister Last weekend I spent time with my 7 ½-year-old daughter (the ½ is crucially important at that age) on our tree house project. Well, it is more a tree “deck” so far, which is quite respectable though given that we just started building it in one weekend (as the book I quickly downloaded that evening on the iPad actually recommended). A project like this gives endles... » read more

Emulation’s Winding Path To Success


By Ed Sperling Emulation was developed for verifying complex ICs when simulation was considered too slow. After more than a decade of very slow growth, however, sales have begun to ramp. There are several reasons for this shift. First, SoCs simply are becoming more complex, and the amount of verification that needs to be done to get a chip out the door can bring simulation to a crawl. Desig... » read more

Emulation 2010


By Ann Steffora Mutschler In an industry that was once fraught with patent infringement lawsuits, hostile takeovers and other exciting corporate warfare, the hardware-assisted emulation market has quieted down considerably. That doesn’t mean it has lost its luster, though. It still plays an integral, if not ever-increasing and expanding, role in the verification efforts of most semiconductor... » read more

Experts At The Table: Rising Complexity Meets Verification


By Ed Sperling Low-Power Engineering sat down to discuss rising complexity and its effects on verification with Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics; Tom Borgstrom, director of solutions marketing at Synopsys; Lauro Rizzatti, vice president of worldwide marketing at EVE, and Prakash Narain, president and CEO Real Intent. What follows are ... » read more

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