The Changing Landscape of Hardware-Based Verification And Software Development

By Frank Schirrmeister - 24 May, 2019 - Comments: 0

As the EDA is gearing up for its biggest industry event, the Design Automation Conference (DAC), this year in Las Vegas, it is interesting to observe what is going on in hardware-based development of emulation and prototyping. The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have only grown stronger and are causing changes in the development landsc... » read more

Three Tools Help Put Safe Vehicles On The Road

By Richard Pugh - 02 May, 2019 - Comments: 0

By Richard Pugh and Gabriele Pulini As the ultimate systems-of-systems, automated vehicles present an enormous verification task, requiring verification of complex sensing, computing, and actuating functions. This can be accomplished only by virtualizing the entire system: the vehicle and the environment it moves through. It also requires a combination of realistic scenario modeling, hard... » read more

Exascale Emulation Debug Challenges

By Ribhu Mittal - 11 Apr, 2019 - Comments: 0

For years, semiconductor industry surveys have shown that functional verification is the dominant phase in chip development and that debug is the most time-consuming task for verification. The problem is getting worse in today’s era of exascale debug, in which software applications drive tests of more than a billion cycles run in emulation on designs of more than a billion gates. System-on-ch... » read more

The Value Of A Model

By Brian Bailey - 28 Mar, 2019 - Comments: 0

Increased talk about the Digital Twin has brought models to the forefront of the discussion. What are the right models for particular applications? What is the correct level of abstraction? Where do the models come from and how are they maintained? How does one value a model? The semiconductor industry has been reluctant to create any model that is not directly used in the development path. ... » read more

Digital Twins For Hardware/Software Co-Development

By Frank Schirrmeister - 28 Mar, 2019 - Comments: 0

These days it seems like we could play business bingo when watching presentations at conferences, checking off the most keywords mentioned. Hitting the terms AI, ML, IoT, 5G, and edge computing all together almost guarantees your presentation to be a hit. In recent years, the term “digital twin” has gotten a lot of attention. Recent discussions with Brian Bailey and a paper I wrote for GOMA... » read more

Digital Twins Deciphered

By Brian Bailey - 28 Mar, 2019 - Comments: 0

Ever since Siemens acquired Mentor Graphics in 2016, a new phrase has become more common in the semiconductor industry – the digital twin. Exactly what that is, and what impact it will have on the semiconductor industry, is less clear. In fact, many in the industry are scratching their heads over the term. The initial reaction is that the industry has been creating what are now termed digi... » read more

Using Less Power At The Same Node

By Brian Bailey - 14 Mar, 2019 - Comments: 0

Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

Can Debug Be Tamed?

By Brian Bailey - 28 Feb, 2019 - Comments: 0

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Designing Networking Chips

By Ed Sperling - 07 Feb, 2019 - Comments: 0

Susheel Tadikonda, vice president of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data. One of those shifts involves software-defined networking, where the greatest complexity resides in the software. That also has a big impact on the entire design flow, from pre-silicon to post-silicon. htt... » read more

Verifying AI Designs Thoroughly And Quickly

By Jean-Marie Brunet - 31 Jan, 2019 - Comments: 0

You can’t turn around these days without seeing a reference to AI – even as a consumer. AI, or artificial intelligence, is hot due to the new machine-learning (ML) techniques that are evolving daily. It’s often cited as one of the critical markets for electronics purveyors, but it’s not really a market: it’s a technology. And it’s quietly – or not so quietly – moving into many, ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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