Secure Interfaces In An Increasingly Connected World

By Dana Neustadter - 03 Nov, 2022 - Comments: 0

The tremendous data and bandwidth growth in the era of supercomputing is driving technological advances across markets and is reshaping system-on-chip (SoC) designs supporting new compute architectures, more acceleration, and more storage. As high bandwidth interfaces including DDR, PCIe, CXL, Ethernet, HDMI and DisplayPort are proliferating and evolving from one generation to another, so does ... » read more

Enabling The Highest Levels Of SoC Security

By Dana Neustadter - 27 Oct, 2022 - Comments: 0

Research Bits: Aug. 8

By Jesse Allen - 08 Aug, 2022 - Comments: 0

Speeding NVM encryption Researchers from North Carolina State University propose a way to speed up encryption and file system performance for non-volatile memory (NVM). “NVMs are an emerging technology that allows rapid access to the data, and retains data even when a system crashes or loses power,” said Amro Awad, an assistant professor of electrical and computer engineering at North C... » read more

Hertzbleed: Prime Time For Power Side Channel Countermeasures Or Novelty Attack?

By Jasper van Woudenberg - 04 Aug, 2022 - Comments: 0

Hertzbleed is a new side-channel attack that turns a power side channel into a timing side channel. That timing side channel may be exploitable even if the algorithm runs in a constant number of clock cycles. The novel observation is that the duration of a clock cycle can vary depending on the data processed on a CPU that uses dynamic frequency scaling. This allows a remote attacker to extract... » read more

“All-in-One” 8×8 Array of Low-Power & Bio-inspired Crypto Engines w/IoT Edge Sensors Based on 2D Memtransistors

By Technical Paper Link - 01 Jul, 2022 - Comments: 0

New technical paper titled "All-in-one, bio-inspired, and low-power crypto engines for near-sensor security based on two-dimensional memtransistors" from researchers at Penn State University. Abstract: "In the emerging era of the internet of things (IoT), ubiquitous sensors continuously collect, consume, store, and communicate a huge volume of information which is becoming increasingly vuln... » read more

The Methods Of Memory Encryption To Protect Data In Use

By Rocky Zhang - 06 Jun, 2022 - Comments: 0

In my blog “The Importance of Memory Encryption for Protecting Data in Use,” I discussed the growing industry consensus on the imperative of incorporating memory encryption in computing architectures. In part two of this series, I’ll explore the cipher algorithms and modes that can be used to protect data stored in and accessed from memory, or in other words, used to protect data in use. ... » read more

SCV (select, cross, and variation): Data Encryption

By Technical Paper Link - 06 May, 2022 - Comments: 0

A new technical paper "RSCV: Reversible Select, cross and variation architecture in quantum-dot cellular automata." Abstract "In the past few years, CMOS semiconductor has been a growing and evolving technology in VLSI. However, due to the scaling issue and some other constraints like heat generation, high power consumption QCA (quantum cellular automata) emerged as an alternate and enhan... » read more

The Importance Of Memory Encryption For Protecting Data In Use

By Rocky Zhang - 05 May, 2022 - Comments: 0

Nowadays, as SoC (System-on-a-Chip) systems become more and more complex, security functions must grow accordingly to protect the semiconductor devices themselves and the sensitive information residing on or passing through them. While a Root of Trust security solution built into the SoCs can protect the chip and data resident therein (data at rest), many other threats exist which target interc... » read more

Hardware Encryption: Ultra-compact Active Interconnect Based on FeFET

By Technical Paper Link - 02 May, 2022 - Comments: 0

New technical paper "Hardware functional obfuscation with ferroelectric active interconnects" from researchers at Penn State, Rochester Institute of Technology, GlobalFoundries Fab1, North Dakota State University. Abstract "Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we... » read more

An End-to-End Bitstream Tamper Attack Against Flip-Chip FPGAs

By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "FPGA bitstream encryption and authentication can be defeated by various techniques and it is critical to understand how these vulnerabilities enable extraction and tampering of commercial FPGA bitstreams. We exploit the physical vulnerability of bitstream encryption keys to readout using failure analysis equipment and conduct an end-to-end bitstream tamper attack. Our work undersco... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?