tag: eSilicon

Consolidation’s Aftermath
By Ed Sperling - 02 Dec, 2015 - Comments: 4

The recent spate of industry consolidation continues to have repercussions across the semiconductor industry. Some of those effects will subside once the deals are either approved or nixed by regulatory agencies. Others will raise questions for months or years to come. Consolidation is not a new trend in the semiconductor industry, but the pace and size of the acquisitions in the past year a... » read more

Memory Choices Grow
By Ed Sperling - 24 Nov, 2015 - Comments: 1

Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization. There are plenty of rules ... » read more

Top Articles For 2015 In SLD And LPHP
By Brian Bailey - 24 Nov, 2015 - Comments: 0

Knowing your readership is the first step in being able to serve them better, and judging by the traffic increases this year, we must be doing quite a few things right. We have now completed our second full year and the first full year for the Knowledge Center (KC). We are pleased with the way in which the two are playing together but there is still a lot of work ahead of and many holes to fill... » read more

Why Packaging Matters
By Ed Sperling - 19 Nov, 2015 - Comments: 1

The semiconductor package is changing. What was until very recently considered an afterthought is now becoming a key part of the design process at all major chipmakers, and a critical factor in the extension of Moore's Law. This is a sharp reversal of what was almost universally an afterthought in planar silicon design and manufacturing. Rarely was the package an integral part of the archite... » read more

More Choices, Less Certainty
By Ed Sperling - 04 Nov, 2015 - Comments: 3

The increasing cost of feature scaling is splintering the chip market, injecting uncertainty into a global supply chain that has been continually fine-tuned for decades. Those with deep enough resources and a clear need for density will likely follow Moore's Law, at least until 7nm. What comes after that will depend on a variety of factors ranging from available lithography—EUV, multi-bea... » read more

The Week In Review: Design/IoT
By Jesse Allen - 30 Oct, 2015 - Comments: 0

Tools Aldec introduced Hybrid Emulation including support for ARM Fast Models. Aldec says the capability to link an SoC emulation hardware platform with a virtual platform allows both software and hardware teams to work on the most up-to-date version of the project, long before first silicon is available, or even much of the RTL or IP has been completed. eSilicon's online quoting tools fo... » read more

Will The Chip Work?
By Ed Sperling - 26 Oct, 2015 - Comments: 0

As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

Will The Chip Work?
By Ed Sperling - 19 Oct, 2015 - Comments: 1

IP is getting better, but the challenges of integrating it are getting worse. As the number of IP blocks in SoCs increases at each new process node, so does the difficulty of making them all work together. In some cases, this can mean extra code and a slight performance hit on power and performance. In other cases, it may require more drastic measures, ranging from a re-spin to a new archite... » read more

Security In 2.5D
By Ed Sperling - 12 Oct, 2015 - Comments: 2

The long-anticipated move to 2.5D and fan-outs is raising some familiar questions about security. Will multiple chips combined in an advanced package be as secure as SoCs where everything is integrated on the same die? The answer isn't a simple yes or no. Put in perspective, all chips are vulnerable to [getkc id="253" kc_name="side channel attacks"], hacking of memory—a risk that increases... » read more

Is The 2.5D Supply Chain Ready?
By Ed Sperling - 28 Sep, 2015 - Comments: 0

A handful of big semiconductor companies began taking the wraps off 2.5D and fan-out packaging plans in the past couple of weeks, setting the stage for the first major shift away from Moore's Law in 50 years. Those moves coincide with reports of commercial [getkc id="82" kc_name="2.5D"] chips from chip assemblers and foundries that are now under development. There have been indications for... » read more

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