Experts At The Table: What’s Next?

By Ed Sperling - 20 Jan, 2014 - Comments: 0

Semiconductor Engineering sat down with Sumit DasGupta, Si2; Simon Bloch, Samsung; Jim Hogan, long-time industry venture capitalist; Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: What’s going to really drive interest in low-power technology? Hogan: The world ... » read more

The Road Ahead For 2014

By Brian Bailey - 16 Jan, 2014 - Comments: 1

Semiconductor Engineering asked several thought leaders in the industry about the market drivers that are affecting their product planning operations for 2014. While almost everyone sees mobile devices continuing to be the major driver during 2014, there are some emerging areas that may start to have a larger impact. This article takes a look at some of those and the impacts they could have on ... » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP

By Ed Sperling - 08 Jan, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: Do we need to move to subsystems or more restri... » read more

Experts At The Table: What’s Next?

By Ed Sperling - 06 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down with Sumit DasGupta, Si2; Simon Bloch, Samsung; Jim Hogan; Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: The future of technology isn’t just about technology. It’s about people and regulations, as well. Where are the hurdles ... » read more

Where Is 2.5D?

By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

Industry Restructures Around Cost

By Ed Sperling - 19 Dec, 2013 - Comments: 1

Talk to any semiconductor executive these days about what’s next for their company and you’ll probably encounter the same perspective—cost will drive future design decisions. Dig a little further, however, and you’ll find no consistent strategy for reducing that cost. While the industry has three very viable solutions for improving the power and performance characteristics of SoCs—... » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP

By Ed Sperling - 12 Dec, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: As more pieces are integrated into complex SoCs... » read more

Is There Light At The End Of Moore’s Tunnel

By Brian Bailey - 22 Nov, 2013 - Comments: 2

Electrons are slow, clumsy and quite easily distracted. They’re slow because it now takes a signal longer to cross a chip than the period of the clock signal. They often don’t travel in straight lines as they collide with other atoms. And electromagnetic interference between adjacent signals can mess with the information they are transferring. On the other hand, light has none of these p... » read more

Even Standard IP Isn’t Always Standard

By Ed Sperling - 21 Nov, 2013 - Comments: 0

Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things: Not all IP works together as planned, even when it’s well characterized. As with cars, performance and mileage vary greatly depending upon who’s driving—and who’s... » read more

Experts At The Table: What’s Next?

By Ed Sperling - 21 Nov, 2013 - Comments: 1

Semiconductor Engineering sat down with Jim Hogan, long-time industry venture capitalist; Simon Bloch, senior director at Samsung Electronics; Sumit DasGupta, formerly Si2 senior vice president of engineering; and Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: What... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: eSilicon

Experts At The Table: What’s Next?

The Road Ahead For 2014

Experts At The Table: Yield And Reliability Issues With Integrating IP

Experts At The Table: What’s Next?

Where Is 2.5D?

Industry Restructures Around Cost

Experts At The Table: Yield And Reliability Issues With Integrating IP

Is There Light At The End Of Moore’s Tunnel

Even Standard IP Isn’t Always Standard

Experts At The Table: What’s Next?