Industry Restructures Around Cost

Over next few years, and certainly the next couple process nodes, the entire chip market will be reshaped.

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Talk to any semiconductor executive these days about what’s next for their company and you’ll probably encounter the same perspective—cost will drive future design decisions. Dig a little further, however, and you’ll find no consistent strategy for reducing that cost.

While the industry has three very viable solutions for improving the power and performance characteristics of SoCs—finFETs, 2.5D and 3D stacked die, and fully depleted silicon on insulator at 28nm, not to mention new types of memories and materials—chipmakers are moving in all of those directions simultaneously, depending on form factor, volume and price resiliency. In some cases, companies are moving in more than one direction for different vertical markets. And in still other cases, they are undecided about which path to take, sitting on the sidelines and waiting for more details to emerge on all of them.

It appears that EDA tools and IP are not sticking points for any of these approaches. In fact, many of the tools—individually and collectively as integrated flows—have been enhanced or revamped to take advantage of all three approaches. So the real issues for chipmakers don’t revolve around whether the tools can do the job. It’s how to achieve the best economies of scale for particular markets, and most of those are related to the supply chain, IP re-use and related standards, as well as lithography and yield.

What’s changing
Behind the scenes, there are a number of factors that are changing that make this a particularly difficult transition.

“We’re coming out of the wireless era, where there were hundreds of companies focused on that,” said Wally Rhines, chairman and CEO of Mentor Graphics. “The next era will be the Internet of Things, where billions and trillions of things are interconnected. We will still need big chips and finFETs for ultra-low power, and we will see 2.5D designs for some companies. For others, 28nm might be the end of the line.”

While no one questions the potential of the Internet of Things, there is some debate about exactly when the wireless era will wind down or how that will happen. At the very least, there will be plenty of churn in coming months.

“The high-end smart phones are about to become PCs, and the low-end smart phones will replace feature phones,” said Charlie Janac, chairman and CEO of Arteris. “What’s going on now is that the mid-range is impacting the high-end. So we’re either going to see another burst of innovation, which is what I believe will happen, or there will be massive cannibalization of the high end of that market. Either way, it will cause a huge amount of dislocation.”

Janac believes that no progress can be made in this market without stacking die because it simply doesn’t make sense to put everything on a 14nm or 10nm die from a cost or performance standpoint. “Right now, mobility is the only market big enough to fill a fab,” he said. “The Internet of Things may be able to do that, although we’re not there yet. But no matter what happens, we need to drop the cost, and process no longer buys a cost reduction.”

Cost reduction is the one point that everyone agrees upon. The question is how to get there, and that’s having a splintering effect. It’s also creating confusion, because the impact is so large and widespread that it’s difficult to wrap your head around it. What happens on a global scale, and in countries such as China, are directly tied to this issue.

“We’re continuing to see slow growth, consolidation and more fragmentation,” said Lip-Bu Tan, president and CEO of Cadence. “But what we’re also beginning to see is the beginning of the China factor. China realizes that semiconductors are essential for their economy and they are pouring money into a whole spectrum, including EDA. Right now China is importing about 59% of its semiconductors.”

He said that, coupled with a push toward system engineering will redefine how the industry looks over the next couple of years. “Chipmakers are facing a lot of the same challenges as EDA. We need smarter designs, first time pass with no respins, and more collaboration. We’re also seeing that the market for startups is very good. That’s where the innovation will happen.”

Architectural shifts
That innovation may have to happen in pieces rather than as a whole design, though, which is why there has been so much interest lately in 2.5D stacked die.

“2.5D has to deliver something big,” said Naveed Sherwani, president and CEO of Open-Silicon. “As an industry we have to make it real and learn from it. People don’t have the money to do 16nm chips. We have to get back to where we were five years ago when you could try different chips at a relatively low cost. And even if half of those chips died, you could still afford to try. Now it’s too expensive to do that.”

He said that with 16nm/14nm finFETs, the only way to enter that market is with high enough volumes to pay for the huge development costs.

He’s not alone in seeing that shift. Jack Harding, president and CEO of eSilicon, said that in the past 12 months there has been a significant shift in chip discussions being elevated to the C-level office from the engineering manager. “When you’re talking about $5 million to $10 million in NRE, that’s a decision for the CEO. There’s a commercial hesitation to drive too hard and too fast. We’re even having more conversations about whether companies want to make their own hardware anymore because they see their value in software and system-level integration. These are chip companies talking about this.”

So what’s next? “My prediction is that a large part of the market will chase packaging technologies,” he said.

The rollout of 2.5D test chips has helped spur some interest in this direction. But that also doesn’t mean that 16/14nm chips are in trouble, either.

“Moore’s Law still has a long way to go,” said Ajit Manocha, CEO of GlobalFoundries. “But it’s not just all about shrinking. We’re also seeing stacking of 2.5D and 3D. The challenge is to bring the cost way down. That’s what we’re working on.”

Complexity fallout
Bringing costs under control also means managing complexity, though, and complexity continues to grow. In fact, many new SoCs it’s exploding. Putting the performance of a PC into a device the size of a smart phone, along with fast connectivity, better security, power management—and a video recorder and MP3 player thrown in—would have been considered science fiction at the beginning of the century.

What made it possible, to a large extent, are massive improvements in EDA tools. But even EDA tools are struggling to keep pace with this shift, not to mention keep costs under control.

“Everything that we expected to see in 2013 with the jump in SoC complexity has taken place because of new silicon nodes and the ever-growing demand for portable consumer electronics,” said Prakash Narain, president and CEO of Real Intent. “EDA vendors have re-engineered their tools to handle what are now giga-gate designs.”

Narain noted that so far the tools are indeed keeping pace with complexity through better integration and methodology “Early verification of all kinds of failure modes—CDC, SDC, power—all of that has moved into RTL functional space and all of them are happening concurrently. We are seeing there is a migration to static solutions to provide a more efficient approach. Once something is defined, static solutions really show their value and get the designer into the fixing process much faster. The challenge in 2014 will be to continue giving signoff-accurate results in hours and not days or weeks.”

Part of the challenge also will be characterizing, qualifying and integrating IP, which can greatly speed time to market.

“There are a lot more IP companies starting up all over the place,” said Srinath Anantharman, CEO of Cliosoft. “We now have 21 customers that sell IP. This has become the new gold rush and the price of the IP has become a big factor. The big question is whether the IP quality will be as good when they’re competing on price.”

And part of it will be dealing with an explosion in data that has come along with that complexity. “What we’re seeing is that because there are multiple sites collaborating on projects, people end up just copying data and sending it every night to the other side like some giant tar ball. The problem is that many times not all of that data is being transferred, so people are afraid to delete it and it just accumulates.”

In the end, all of this comes back to cost, which is a function of manufacturability, time to market, power management, more efficient architectures, faster and better tools and methodologies, and incessant demands by consumers and businesses for much more capability for less money. The question is how best to satisfy all of these needs, and so far there is no clear answer.



1 comments

Kurt Shuler says:

This article I wrote yesterday also brings up the point of packaging technology replacing transistor technology as an innovation driver. My analysis is based on partly in the McKinsey Insight article, “Moore’s Law: Repeal or Renewal?” My article: http://semiengineering.com/industry-shaking-changes-ahead/, McKinsey article: http://www.mckinsey.com/Insights/High_Tech_Telecoms_Internet/Moores_law_Repeal_or_renewal

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