tag: eSilicon

De-Mystifying The SoC Supply Chain
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Barbara Jorgensen At the heart of every supply chain operation is the desire to mitigate risk. In theory, a supply chain allows a customer to leverage the best of the best in technology, logistics or production at a lower cost than DIY (do it yourself.) The system on chip (SoC) supply chain is no different—there’s a whole ecosystem in the semiconductor industry that supports design, pro... » read more

Experts At The Table: Nice To Have Vs. Need To Have
By Ed Sperling - 10 Jun, 2013 - Comments: 0

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation. LPE... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 09 Feb, 2013 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

Executive Outlook
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ed Sperling The view from the top of companies is a like a high-level of abstraction for viewing the industry. While engineers get caught up in individual projects, or pieces of projects, CEOs and CTOs tend to see things from a much broader perspective. So what do they see as the big issues and developments over the next 12 to 24 months? System-Level Design asked industry leaders that q... » read more

Experts At The Table: The Business Of IP
By Ed Sperling - 26 Oct, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss IP supply chain issues with Jim Hogan, an independent VC; Jack Brown, senior vice president at Sonics; Mike Gianfagna, vice president of marketing at Atrenta; Paul Hollingworth, vice president of strategic accounts at eSilicon, and Warren Savage, CEO of IPextreme. What follows are excerpts of that conversation. LPHP:... » read more

Experts At The Table: The Business Of IP
By Ed Sperling - 19 Oct, 2012 - Comments: 0

Low-Power/High-Performance Engineering sat down to discuss IP supply chain issues with Jim Hogan, an independent VC; Jack Brown, senior vice president at Sonics; Mike Gianfagna, vice president of marketing at Atrenta; Paul Hollingworth, vice president of strategic accounts at eSilicon, and Warren Savage, CEO of IPextreme. What follows are excerpts of that conversation. LPHP: There’s so muc... » read more

Experts at the Table: Black Belt Power Management
By Ann Mutschler - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Low-Power/High-Performance Engineering sat down to discuss rising integration challenges caused by an increasing amount of black-box IP with Qi Wang, technical marketing group director, solutions marketing, for the low-power and mixed-signal group at Cadence; J. Bhasker, architect at eSilicon Corp.; Navraj Nandra, senior director of product marketing for analog an... » read more

Inflection Points Ahead
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

Experts At The Table: Black Belt Power Management
By Ann Mutschler - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler With approximately 80% of SoC content reused from past designs or brought in from internal and external IP sources, a significant part of a design engineer’s job today is writing glue logic and verifying to make sure the integrated system communicates as dictated by the specification. Integration challenges continue to mount with the increasing amount of black ... » read more

Managing Complexity With Advanced Packaging
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ann Steffora Mutschler Engineering teams across the globe continue to pound the process geometry treadmill to stay on the curve of Dr. Moore to achieve better speed or lower power or smaller die—and it all adds up to increased complexity in the design and packaging. However, with advanced forms of die stacking such as package-on-package, silicon-in-package, 2.5D silicon interposer techno... » read more

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