Chip Industry Week In Review
Onsemi to buy Synaptics; IBM's 7Å chip w/40% more SRAM area; 1nm MoS2 nanotubes; AI pressure points; memory updates; $250M CHIPS Act award; trade secret theft; new advanced packaging site; MEMS capacity; humanoids; earnings.
Executive Outlook: Agentic AI’s Impact On Chip Design
Can engineers trust AI to get everything right in semiconductor design and verification?
Chip Industry Week In Review
S. Korea goes All In on AI; new Dresden power fab; Intel expansion; GM secures memory supply; AI power management funding; mature-node foundry capacity; 300mm fab equipment; McKinsey's map of strategic IC supply; security threats; AI burnout.
I/O Design Challenges Grow In AI Data Centers And HPC Clusters
Physical I/Os can be a chokepoint for high-performance chips and high-speed interconnect protocols, requiring design tradeoffs and extra reliability measures.
Chip Industry Week In Review
Apple-Intel is on, says Trump; Amkor's big win; Intel 18A-P; Amazon to sell its AI chips; Rambus' automotive RoT; Brewer's buy; VLSI Symposium tech; CHIPS Act funding; MIT sensor; RISC-V CPU fuzzing.
Flash Getting Stacked High-Bandwidth Version
Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.
Can Edge AI Keep Up?
As models evolve faster than silicon cycles, experts weigh how much adaptability architects can afford without sacrificing power, area, or efficiency.
Chiplets Need A New Workflow
Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.
Agentic AI Is Changing Data Center Architectures
Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory bottlenecks, reduce latency, and boost efficiency.
Gates Add Functionality, But Wires Create Problems
Wires are treated as a lesser concern, but their neglect is becoming critical at advanced nodes.
A New Era For Co-Processing
Processor architectures are evolving faster than ever, but they still lag the pace of AI development. Chip architects must predict what will be required tomorrow in designs today.
PCIe Benefits From AI, Despite Scaling Protocols
CXL is also gaining traction in AI processing, while MIPI and others are growing at the edge.
DRAM’s Whac‑A‑Mole Security Crisis
New refresh commands chase Rowhammer and Rowpress, but a permanent fix remains years away.
