The Sub-2nm Paradox
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
AI Accelerator Testing Depends On DFT Innovations
Multi-die assemblies greatly increase the number of things that can go wrong, and the difficulty of finding them.
Flash Getting Stacked High-Bandwidth Version
Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.
Chiplets Need A New Workflow
Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.
Chip Industry Week In Review
Taiwan, Europe packaging buildout; 2nm ramps; quantum big $; 2 new university hubs; agent honeypots; Samsung strike averted; extreme environment chip design; quantum-dot qubit device fabricated w/high-NA EUV; EU flagship power electronics project; CNTs.
CPO Is Extending The Limits Of What’s Possible In AI Data Centers
Co-packaged optics technology will have a big impact on system power and the cost of data movement.
Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges
Reliability is now a system-level concern that includes everything from materials and packaging to testing with backside power.
UCIe’s Major Technical Components Are Now In Place
Version 3.0 of the interconnect standard doubles bandwidth and supports new use cases and enhanced manageability.
The On-Device LLM Revolution
Why 3B to 30B models are moving to the edge — and what that means for silicon.
Can Edge AI Keep Up?
As models evolve faster than silicon cycles, experts weigh how much adaptability architects can afford without sacrificing power, area, or efficiency.
Flash Getting Stacked High-Bandwidth Version
Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.
Chiplets Need A New Workflow
Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.
Minimum Energy Per Query
How much of the energy consumed in an AI chip is spent doing something useful? This question affects everything from software to system architecture to chip design.
