CPO Is Extending The Limits Of What’s Possible In AI Data Centers
Co-packaged optics technology will have a big impact on system power and the cost of data movement.
Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges
Reliability is now a system-level concern that includes everything from materials and packaging to testing with backside power.
UCIe’s Major Technical Components Are Now In Place
Version 3.0 of the interconnect standard doubles bandwidth and supports new use cases and enhanced manageability.
Can Edge AI Keep Up?
As models evolve faster than silicon cycles, experts weigh how much adaptability architects can afford without sacrificing power, area, or efficiency.
Flash Getting Stacked High-Bandwidth Version
Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.
Chiplets Need A New Workflow
Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.
Minimum Energy Per Query
How much of the energy consumed in an AI chip is spent doing something useful? This question affects everything from software to system architecture to chip design.
AI Power on the Edge
Architecting solutions for edge AI is not about minimizing cloud solutions or making small extensions of existing MCUs/MPUs. It's a hardware/software/model co-development problem.
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