tag: EUV

Manufacturing Bits: Dec. 15
By Mark LaPedus - 15 Dec, 2015 - Comments: 0

DRAM scaling sans EUV At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., chipmakers presented papers on several technologies, including one unlikely topic—DRAM scaling. For years, it was believed that DRAMs would hit the wall and stop scaling at 20nm or so. Then, at that point, the industry would need to migrate to a 3D DRAM structure or a next-generatio... » read more

The Pain Of Change
By Ed Sperling - 24 Nov, 2015 - Comments: 0

If the still evolving shift left has taught the semiconductor industry anything, it's that nothing can be counted on to stay the same for very long. The basic proposition of doing more earlier in the design cycle to speed up time to market—and thereby shifting everything left in the linear flow—means that every silo that has been constructed over the past several decades needs to be rethoug... » read more

Can Nano-Patterning Save Moore’s Law?
By Mark LaPedus - 19 Nov, 2015 - Comments: 0

For years the academic community has explored a novel technology called selective deposition. Then, more than a year ago, Intel spearheaded an effort to bring the technology from the lab to the fab at 7nm or 5nm. Today, selective deposition is still in R&D, but it is gaining momentum in the industry. With R&D funding from Intel and others, selective deposition, sometimes called ALD-e... » read more

Inside Multi-Beam E-Beam Lithography
By Mark LaPedus - 19 Nov, 2015 - Comments: 4

Semiconductor Engineering sat down with David Lam, chairman of Multibeam, a developer of multi-beam e-beam tools for direct-write lithography applications. Lam is also a venture capitalist. He founded Lam Research in 1980, but left as an employee in 1985. What follows are excerpts of that conversation. SE: How has the equipment business changed over the years and what’s the state of the i... » read more

What’s Really Causing Line-Edge Roughness?
By Katherine Derbyshire - 19 Nov, 2015 - Comments: 0

As previously discussed, shot noise is an important contributor to line edge roughness. However, as the title of one paper on the subject put it, “Do not always blame the photons.” The line edge roughness of a chemically amplified resist ultimately depends on photoacid generation and the deprotection of the resist’s base monomers. Photons absorbed by the resist simply trigger a chain ... » read more

More Choices, Less Certainty
By Ed Sperling - 04 Nov, 2015 - Comments: 3

The increasing cost of feature scaling is splintering the chip market, injecting uncertainty into a global supply chain that has been continually fine-tuned for decades. Those with deep enough resources and a clear need for density will likely follow Moore's Law, at least until 7nm. What comes after that will depend on a variety of factors ranging from available lithography—EUV, multi-bea... » read more

The Next Resists
By Katherine Derbyshire - 22 Oct, 2015 - Comments: 5

As EUV exposure tools, sources, and photomasks have become more capable, the lithography sector’s attention has turned to EUV photoresist. After all, once the exposure system can produce a high quality image at the wafer, the resist still has to capture it for pattern transfer. Unfortunately, the increasing emphasis on photoresist has made the limitations of current formulations even more obv... » read more

Increasing Challenges At Advanced Nodes
By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

Taming Mask Metrology
By Mark LaPedus - 22 Oct, 2015 - Comments: 0

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

First Look: 5nm
By Ann Mutschler - 15 Oct, 2015 - Comments: 3

By the time the 5nm semiconductor manufacturing process node reaches mass production readiness, the hurdles and challenges will no longer be open for discussion. But as of this moment, some of them seem almost insurmountable, raising new questions about the continued viability of Moore's Law. There has been much written about the end of [getkc id="74" comment="Moore's Law"] for nearly two de... » read more

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