Everyone’s A System Designer With Heterogeneous Integration

By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Application-Optimized Processors

By Ed Sperling - 29 Sep, 2023 - Comments: 0

Executing a neural network on top of an NPU requires an understanding of application requirements, such as latency and throughput, as well as the potential partitioning challenges. Sharad Chole, chief scientist and co-founder of Expedera, talks about fine-grained dependencies, why processing packets out of order can help optimize performance and power, and when to use voltage and frequency scal... » read more

Patterns And Issues In AI Chip Design

By Ed Sperling - 14 Sep, 2023 - Comments: 2

AI is becoming more than a talking point for chip and system design, taking on increasingly complex tasks that are now competitive requirements in many markets. But the inclusion of AI, along with its machine learning and deep learning subcategories, also has injected widespread confusion and uncertainty into every aspect of electronics. This is partly due to the fact that it touches so many... » read more

Generative AI: Transforming Inference At The Edge

By Paul Karazuba - 24 Aug, 2023 - Comments: 0

The world is witnessing a revolutionary advancement in artificial intelligence with the emergence of generative AI. Generative AI generates text, images, or other media responding to prompts. We are in the early stages of this new technology; still, the depth and accuracy of its results are impressive, and its potential is mind-blowing. Generative AI uses transformers, a class of neural network... » read more

An Ideal Architecture For Always-On Camera Subsystems

By Expedera - 23 Aug, 2023 - Comments: 0

Always-sensing camera implementations offer a wealth of user experience advantages but face significant power, latency, and privacy concerns if not done right. To be successful, always-sensing camera subsystems must be architected to preserve battery life and to ensure privacy and security while delivering key user experience improvements. In a joint white paper with Rambus, Expedera discuss... » read more

A Packet-Based Architecture For Edge AI Inference

By Pat Donnelly - 27 Jul, 2023 - Comments: 0

Despite significant improvements in throughput, edge AI accelerators (Neural Processing Units, or NPUs) are still often underutilized. Inefficient management of weights and activations leads to fewer available cores utilized for multiply-accumulate (MAC) operations. Edge AI applications frequently need to run on small, low-power devices, limiting the area and power allocated for memory and comp... » read more

The Road Ahead For SoCs In Self-Driving Vehicles

By Expedera - 26 Jul, 2023 - Comments: 0

Automakers have relied on a human driver behind the wheel for more than a century. With Level 3 systems in place, the road ahead leads to full autonomy and Level 5 self-driving. However, it’s going to be a long climb. Much of the technology that got the industry to Level 3 will not scale in all the needed dimensions — performance, memory usage, interconnect, chip area, and power consumption... » read more

Week In Review: Auto, Security, Pervasive Computing

By Liz Allan - 21 Jul, 2023 - Comments: 0

The Biden-Harris Administration announced the U.S. Cyber Trust Mark, a cybersecurity certification and labeling program to help consumers choose smart devices less vulnerable to cyberattacks. The Federal Communications Commission (FCC) is applying to register the Cyber Trust Mark with the U.S. Patent and Trademark Office and it would appear on qualifying smart products, including refrigerators,... » read more

Week In Review: Design, Low Power

By Jesse Allen - 21 Jul, 2023 - Comments: 0

Cadence will acquire Rambus' SerDes and memory interface PHY IP business. Rambus will retain its digital IP business, including memory and interface controllers and security IP. “With this transaction, we will increase our focus on market-leading digital IP and chips and expand our roadmap of novel memory solutions to support the continued evolution of the data center and AI,” said Sean Fan... » read more

Week In Review: Auto, Security, Pervasive Computing

By Liz Allan - 30 Jun, 2023 - Comments: 0

Inflection AI raised $1.3 billion in a new funding round led by Microsoft, Reid Hoffman, Bill Gates, Eric Schmidt, and NVIDIA after raising $225 million in the first round to support the ongoing development of Pi, a “useful, friendly, and fun” AI. In partnership with CoreWeave and NVIDIA, Inflection aims to build the world’s largest AI cluster, comprised of 22,000 NVIDIA H100 Tensor Core ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Expedera

Everyone’s A System Designer With Heterogeneous Integration

Application-Optimized Processors

Patterns And Issues In AI Chip Design

Generative AI: Transforming Inference At The Edge

An Ideal Architecture For Always-On Camera Subsystems

A Packet-Based Architecture For Edge AI Inference

The Road Ahead For SoCs In Self-Driving Vehicles

Week In Review: Auto, Security, Pervasive Computing

Week In Review: Design, Low Power

Week In Review: Auto, Security, Pervasive Computing