tag: fan-outs

Plotting The Next Semiconductor Road Map
By Ed Sperling - 13 Jun, 2016 - Comments: 0

The semiconductor industry is retrenching around new technologies and markets as Moore's Law becomes harder to sustain and growth rates in smart phones continue to flatten. In the past, it was a sure bet that pushing to the next process node would provide improvements in power, performance and cost. But after 22nm, the economics change due to the need for multi-patterning and finFETs, and th... » read more

Power-Centric Chip Architectures
By Ed Sperling - 12 May, 2016 - Comments: 0

As traditional scaling runs out of steam, new chip architectures are emerging with power as the starting point. While this trend has been unfolding for some time, it is getting an extra boost and sense of urgency as design teams weigh a growing number of design challenges and options across a variety of new markets. Among the options are [getkc id="196" kc_name="multi-patterning"] and [getkc... » read more

Why This Roadmap Matters
By Ed Sperling - 05 May, 2016 - Comments: 0

The semiconductor industry is now officially looking beyond PCs and servers, establishing metrics and guidance for existing and developing market segments rather than just focusing on how to get to the next process nodes. The IEEE's International Roadmap for Devices and Systems marks a fundamental shift in the industry. The uncertainty that has ensued ever since the introduction of 3D transi... » read more

End Of Mixed Signal Engineering?
By Ed Sperling - 04 May, 2016 - Comments: 1

EDA companies are stepping back after years of trying to force engineers to combine analog and digital disciplines. Rather than emphasizing [getkc id="38" kc_name="mixed signal"] as a single expertise, they are building bridges and translation mechanisms between the two worlds. The moves cap more than a decade of trying to find optimal ways to pack [getkc id="37" kc_name="analog"] and digita... » read more

Foundries Expand Their Scope
By Ed Sperling - 21 Apr, 2016 - Comments: 0

By Ed Sperling & Mark LaPedus Major foundries are stepping up their offerings across a wide swath of technology nodes, specialty processes and advanced packaging—a recognition that end markets are fragmenting and that the path forward includes a mix of new and established processes. As the smart phone market flattens, there is no single "next big thing" to drive volume at the most ... » read more

2.5D Becomes A Reality
By Ed Sperling - 14 Apr, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

How Many Cores? (Part 2)
By Ed Sperling - 21 Mar, 2016 - Comments: 1

New chip architectures and new packaging options—including fan-outs and 2.5D—are changing basic design considerations for how many cores are needed, what they are used for, and how to solve some increasingly troublesome bottlenecks. As reported in part one, just adding more cores doesn't necessarily improve performance, and adding the wrong size or kinds of cores wastes power. That has s... » read more

Inside The OSAT Business
By Mark LaPedus - 17 Mar, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the IC-packaging industry, foundries, China and other topics with Tien Wu, chief operating officer at Taiwan's Advanced Semiconductor Engineering (ASE), the world's largest outsourced semiconductor assembly and test (OSAT) vendor. What follows are excerpts of that conversation. SE: What is your overall outlook for 2016? Wu: Last year, the semi... » read more

New Memory Approaches And Issues
By Ed Sperling - 14 Mar, 2016 - Comments: 1

New memory types and approaches are being developed and tested as DRAM and Moore's Law both run out of steam, adding greatly to the confusion of what comes next and how that will affect chip designs. What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes. New architectures, such as [getkc id="202" kc_name="fan-outs"] and [getk... » read more

Racing To Design Chips Faster
By Ed Sperling - 25 Feb, 2016 - Comments: 6

A shift is underway to develop chips for more narrowly defined market segments, and in much smaller production runs. Rather than focusing on shrinking features and reducing cost per transistor by the billions of units, the emphasis behind this shift is less about scale and much more about optimization for specific markets and delivering those solutions more quickly. As automotive, consumer e... » read more

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