FeFET Multi-Level Cells For In-Memory Computing In 28nm


A technical paper titled “First demonstration of in-memory computing crossbar using multi-level Cell FeFET” was published by researchers at Robert Bosch, University of Stuttgart, Indian Institute of Technology Kanpur, Fraunhofer IPMS, RPTU Kaiserslautern-Landau, and Technical University of Munich. Abstract: "Advancements in AI led to the emergence of in-memory-computing architectures as a... » read more

Reservoir Computing HW Based on a CMOS-Compatible FeFET


A new technical paper titled "Reservoir computing on a silicon platform with a ferroelectric field-effect transistor" was published by researchers at the University of Tokyo. Researchers report "reservoir computing hardware based on a ferroelectric field-effect transistor (FeFET) consisting of silicon and ferroelectric hafnium zirconium oxide. The rich dynamics originating from the ferroelec... » read more

Hardware Encryption: Ultra-compact Active Interconnect Based on FeFET


New technical paper "Hardware functional obfuscation with ferroelectric active interconnects" from researchers at Penn State, Rochester Institute of Technology, GlobalFoundries Fab1, North Dakota State University. Abstract "Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we... » read more