tag: finFET

Week In Review: Manufacturing, Design, Test
By Mark LaPedus - 24 Jan, 2014 - Comments: 0

Look for a nasty political campaign in Idaho, according to Bloomberg. Business leaders from Micron Technology and others in Idaho are endorsing the incumbent Republican candidate over a Tea Party challenger. The challenger, Bryan Smith, is a conservative Republican running for Idaho’s second congressional district. He is running against 16-year incumbent Mike Simpson. Simpson is supposedly pr... » read more

Mixed Signals Seen For Fab Tool Industry
By Mark LaPedus - 14 Jan, 2014 - Comments: 2

After a slight downturn in 2013, the semiconductor equipment market is expected to rebound and see solid growth in 2014, according to forecasters at SEMI’s Industry Strategy Symposium (ISS) at Half Moon Bay, Calif. Gartner, IC Insights and VLSI Research separately projected strong growth in the fab tool industry in 2014. But on the downside, the number of large fab tool buyers continues to... » read more

Manufacturing Bits: Dec. 17
By Mark LaPedus - 17 Dec, 2013 - Comments: 0

Implantable TFETs At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., a number of companies, R&D organizations and universities described new breakthroughs in perhaps the next big thing in semiconductors--the tunnel field-effect transistor (TFET). Aimed for the 5nm node, TFETs are steep sub-threshold slope transistors that can scale the supply voltages bel... » read more

The “Last Simple Node” And the Internet of Things
By Brian Fuller - 17 Oct, 2013 - Comments: 0

Power, performance and size are key targets that will enable the expected explosion of the Internet of Things (IoT). Today, most observers see the path to that running directly through 16/14nm finFET and below for the node’s ability to manage power and size and boost integration. Geoff Lees isn’t your average observer. The vice president and general manager of Freescale’s microcon... » read more

Power Grid Analysis Heats Up At 20nm
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Do a simple Internet search for the term ‘power grid analysis’ and most of the results are academic sources. However, given the physics of either planar or finFET at 20nm and below, the power grid will see significant impacts. Overall, there are a number of technical implications of migrating from 28nm down to 20, 16 or 14 nm, with further impacts of moving fro... » read more

Mixed Signals
By Mark LaPedus - 08 Jul, 2013 - Comments: 0

By Mark LaPedus Based on the various forecasts for semiconductor equipment, the mood is mixed at this week’s Semicon West trade show in San Francisco. In its mid-year forecast, for example, SEMI predicts that the semiconductor equipment market will reach $36.3 billion in 2013, down 1.7% over 2012. But the business is expected to rebound and reach $43.98 billion in 2014, a 21.2 percent inc... » read more

VLSI Kyoto – The SOI Papers
By Various Writers - 19 Jun, 2013 - Comments: 0

By Adele Hars There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions.  The papers should all b... » read more

FinFET Isolation: Bulk vs. SOI
By Various Writers - 15 May, 2013 - Comments: 1

Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI.  It generated immense interest, and created lots of discussion on various LinkedIn groups.  In case you missed it, here it is again. (This article is based on an in-depth presentation Terry gave at the SOI Consortium's Fully-Depleted Tech Workshop, held during VLSI-TSA in Taiwan, April 2... » read more

Design Topology Requires Physical Data
By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

The Power Game
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor engineering teams always have focused on stepping up performance in new designs, but in the mobile, GPU and tablet markets they’re finding that maintaining the balance between higher performance and the same or lower power is increasingly onerous. The reason: Extreme gaming applications can create scenario files that cause dynamic power consumpt... » read more

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