tag: formal verification

More Sigmas In Auto Chips
By Ann Mutschler - 02 Aug, 2018 - Comments: 0

The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems. This includes everything from new requirements for automotive-grade chips to longer mean time between failures. But it also makes it far more challenging, time-consuming and complicated to create these d... » read more

Why Parallelization Is So Hard
By Brian Bailey - 30 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Design Verification Is All About Good Hygiene
By OneSpin Solutions - 25 Jul, 2018 - Comments: 0

Design verification has a lot in common with human hygiene practices. The goal of both activities is to remove all dirt, grime, and bugs through an active process of establishing good hygiene. If this process is not followed properly, the result is viruses, infections, and other illnesses. Good verification hygiene is as important in semiconductor development as human hygiene is for a healthy b... » read more

Verification As A Flow (Part 3)
By Brian Bailey - 24 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

ISO 26262 Statistics
By Ed Sperling - 02 Jul, 2018 - Comments: 0

Jorg Gosse, functional safety product manager at OneSpin Solutions, talks about the statistics behind the standards, what is considered good enough, and how those numbers vary across different standards. https://youtu.be/cNTFN3kQ-OM » read more

Formal Abstraction And Coverage
By Brian Bailey - 28 Jun, 2018 - Comments: 0

For the past three years, Oski Technology has facilitated a gathering of formal verification experts over dinner to discuss the problems and issues that they face. They discuss techniques they have been attempting with formal verification technologies, along with the results they have been achieving. Semiconductor Engineering was there to record that conversation and to condense it into the ... » read more

FPGAs Becoming More SoC-Like
By Ann Mutschler - 04 Jun, 2018 - Comments: 1

FPGAs are blinged-out rockstars compared to their former selves. No longer just a collection of look-up tables (LUTs) and registers, FPGAs have moved well beyond into now being architectures for system exploration and vehicles for proving a design architecture for future ASICs. This family of devices now includes everything from basic programmable logic all the way up to complex SoC devices.... » read more

Get Ready For Verification 3.0
By Brian Bailey - 24 May, 2018 - Comments: 0

Jim Hogan, managing partner of Vista Ventures, LLC, is perhaps the best-known investor in the EDA space. Recently, he has been focusing time and attention on verification startups, including cloud technology company Metrics, and Portable Stimulus pioneer Breker Verification Systems. This adds to his longer-term commitment to formal verification with OneSpin Solutions. These companies are part ... » read more

Tech Talk: Traceability In Functional Safety
By Ed Sperling - 24 May, 2018 - Comments: 0

Dominik Strasser, vice president of engineering at OneSpin Solutions, talks about the impact of functional safety regulations on liability and traceability in automotive, rail, industrial, nuclear and machinery applications. https://youtu.be/2jWnId8jQJg » read more

Finding And Fixing ML’s Flaws
By Ed Sperling - 02 May, 2018 - Comments: 0

OneSpin CEO Raik Brinkmann sat down with Semiconductor Engineering to discuss how to make machine learning more robust, predictable and consistent, and new ways to identify and fix problems that may crop up as these systems are deployed. What follows are excerpts of that conversation. SE: How do we make sure devices developed with machine learning behave as they're supposed to, and how do we... » read more

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