Modification Of An Existing E-Graph Based RTL Optimization Tool As A Formal Verification Assistant


A technical paper titled “Datapath Verification via Word-Level E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. Abstract: "Formal verification of datapath circuits is challenging as they are subject to intense optimization effort in the design phase. Industrial vendors and design companies deploy equivalence checking against a golden or exi... » read more

Hardware-Efficient Approach To Defend Against Fault Attacks


A technical paper titled "Fault Attacks on Access Control in Processors: Threat, Formal Analysis and Microarchitectural Mitigation" was published by researchers at University of Kaiserslautern-Landau. Abstract: "Process isolation is a key component of the security architecture in any hardware/software system. However, even when implemented correctly and comprehensively at the software (SW) le... » read more

Welcome To EDA 4.0 And The AI-Driven Revolution


By Dan Yu, Harry Foster, and Tom Fitzpatrick Welcome to the era of EDA 4.0, where we are witnessing a revolutionary transformation in electronic design automation driven by the power of artificial intelligence. The history of EDA can be delineated into distinct periods marked by significant technological advancements that have propelled faster design iterations, improved productivity, and fu... » read more

Chips Getting More Secure, But Not Quickly Enough


Experts at the Table: Semiconductor Engineering sat down to talk about the impact of heterogeneous integration, more advanced RISC-V designs, and a growing awareness of security threats, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketin... » read more

Hybrid Hardware Fuzzer, Combining Capabilities of Formal Verification Methods And Fuzzing Tools


A new technical paper titled "HyPFuzz: Formal-Assisted Processor Fuzzing" was published by researchers at Texas A&M University and Technische Universität Darmstadt. Abstract: "Recent research has shown that hardware fuzzers can effectively detect security vulnerabilities in modern processors. However, existing hardware fuzzers do not fuzz well the hard-to-reach design spaces. Consequently,... » read more

AI Becoming More Prominent In Chip Design


Semiconductor Engineering sat down to talk about the role of AI in managing data and improving designs, and its growing role in pathfinding and preventing silent data corruption, with Michael Jackson, corporate vice president for R&D at Cadence; Joel Sumner, vice president of semiconductor and electronics engineering at National Instruments; Grace Yu, product and engineering manager at Meta... » read more

Using Formal Verification To Optimize HLS-Produced Circuits (ETH Zurich)


A new technical paper titled "Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking" was published by researchers at ETH Zurich. Abstract "Recent HLS efforts explore the generation of dynamically scheduled, dataflow circuits from high-level code; their ability to adapt the schedule at runtime to particular data and control outcomes promises superior performance to standar... » read more

Agile HW Design: Fully Automatic Equivalence Checking Workflow


A new technical paper titled "An Equivalence Checking Framework for Agile Hardware Design" was published by researchers at Portland State University and Intel. Abstract "Agile hardware design enables designers to produce new design iterations efficiently. Equivalence checking is critical in ensuring that a new design iteration conforms to its specification. In this paper, we introduce an eq... » read more

Formal Verification Of AI Processor Datapaths In Automotive Applications


There aren’t many electronic applications that require correctness, safety, and security more than automobiles and other road vehicles. Owners rely on their cars operating properly and reliably at all times. The very lives of drivers, passengers, and those nearby are at risk if a vehicle misbehaves. The situation grows more serious with every innovation in automotive electronics. With a mo... » read more

Capability Hardware Enhanced RISC Instructions (CHERI) For Verification, With Better Memory Safety (Oxford)


A technical paper titled "A Formal CHERI-C Semantics for Verification" was published by researchers at University of Oxford. Abstract: "CHERI-C extends the C programming language by adding hardware capabilities, ensuring a certain degree of memory safety while remaining efficient. Capabilities can also be employed for higher-level security measures, such as software compartmentalization, ... » read more

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