tag: formal

Why Your FPGA Synthesis Flow Requires Verification
By Tom Anderson - 26 Apr, 2018 - Comments: 0

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requir... » read more

Asterix In The Land Of Sudoku: The Fast, The Elegant, And The Popular Formal Solvers
By Sergio Marchese - 22 Mar, 2018 - Comments: 0

It has become a time-honored tradition for OneSpin to pose a holiday puzzle challenge to engineers everywhere. Last year, we asked you to solve the famous Einstein riddle using assertions and a formal tool: It was a great success. For the 2017–18 holiday season, we asked you to solve the hardest Sudoku in the world and prove that the solution is unique. We are delighted that even more enthusi... » read more

Making Sense Of Safety Standards
By Tom Anderson - 22 Feb, 2018 - Comments: 0

If you’re involved in the design or verification of safety-critical electronics, you’ve probably heard about some of the standards that apply to such development projects. If not, then you’re probably puzzled when you read about TÜV SÜD certifying that an EDA tool satisfies functional safety standards ISO 26262 (TCL3/ASIL D), IEC 61508 (T2/SIL 3) and EN 50128 (T2/SIL 3). The industry ha... » read more

Formal In The Spotlight
By Sergio Marchese - 25 Jan, 2018 - Comments: 0

Who doesn’t like a great family picture during the festive season? Of course, those occasions call for reasonably elegant attire. When in the spotlight, most people like to get somewhat more formal. It seems that in the semiconductor world, it’s the reverse. As formal verification transitioned from a niche technology to mainstream over the past few years, formal verification engineers an... » read more

Using Formal To Solve The World’s Hardest Sudoku
By Saša Stamenković - 21 Dec, 2017 - Comments: 0

It’s no secret that the OneSpin team loves contests. Last year around this time, we set a challenge to engineers everywhere: solve the famous Einstein’s Riddle using a formal tool. After an enthusiastic response, we decided to make the holiday puzzle an annual event, with a different subject area each year. Our engineering team was challenged to come up with a new topic, and my idea, whi... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2017 - Comments: 0

Mentor's Andrew Macleod points out five things that need to happen for autonomous and electric cars to move from R&D and test cases to mass-produced, commercially viable vehicles. Synopsys' Iain Singleton provides some tips on tackling large designs with formal and how the assume-guarantee technique helps split them without masking bugs. Cadence's Paul McLellan shares updates from the... » read more

Blog Review: Dec. 13
By Jesse Allen - 13 Dec, 2017 - Comments: 0

Mentor's Sherif Hany notes that pattern matching isn't just for litho hotspots anymore, and is increasingly being used in a wide range of early design phase checks, DRC flows, layout retargeting and fixing and DFM checks. Synopsys' Eric Huang explains why USB cables have gotten so short, even though no length is mentioned in the specification. Cadence's Paul McLellan listens in as Jeremy ... » read more

Blog Review: Nov. 15
By Jesse Allen - 15 Nov, 2017 - Comments: 0

Cadence's Paul McLellan shares highlights from the Jasper User Group, including what to do when formal is not converging on a proof and formal in use at Arm. Synopsys' Anders Nordstrom explains how formal can verify SoC interconnects and get you from San Jose to Austin. Mentor's Jeff Miller argues that intelligent sensors are the basic building block for the IoT, and the market is growing... » read more

Which Verification Engine?
By Ed Sperling - 01 Nov, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

How To Handle Concurrency
By Brian Bailey - 30 Oct, 2017 - Comments: 3

The evolution of processing architectures has solved many problems within a chip, but for each problem solved another one was created. Concurrency is one of those issues, and it has been getting much more attention lately. While concurrency is hardly a new problem, the complexity of today’s systems is making it increasingly difficult to properly design, implement and verify the software an... » read more

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