tag: formal

Formal In The Spotlight
By Sergio Marchese - 25 Jan, 2018 - Comments: 0

Who doesn’t like a great family picture during the festive season? Of course, those occasions call for reasonably elegant attire. When in the spotlight, most people like to get somewhat more formal. It seems that in the semiconductor world, it’s the reverse. As formal verification transitioned from a niche technology to mainstream over the past few years, formal verification engineers an... » read more

Using Formal To Solve The World’s Hardest Sudoku
By Saša Stamenković - 21 Dec, 2017 - Comments: 0

It’s no secret that the OneSpin team loves contests. Last year around this time, we set a challenge to engineers everywhere: solve the famous Einstein’s Riddle using a formal tool. After an enthusiastic response, we decided to make the holiday puzzle an annual event, with a different subject area each year. Our engineering team was challenged to come up with a new topic, and my idea, whi... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2017 - Comments: 0

Mentor's Andrew Macleod points out five things that need to happen for autonomous and electric cars to move from R&D and test cases to mass-produced, commercially viable vehicles. Synopsys' Iain Singleton provides some tips on tackling large designs with formal and how the assume-guarantee technique helps split them without masking bugs. Cadence's Paul McLellan shares updates from the... » read more

Blog Review: Dec. 13
By Jesse Allen - 13 Dec, 2017 - Comments: 0

Mentor's Sherif Hany notes that pattern matching isn't just for litho hotspots anymore, and is increasingly being used in a wide range of early design phase checks, DRC flows, layout retargeting and fixing and DFM checks. Synopsys' Eric Huang explains why USB cables have gotten so short, even though no length is mentioned in the specification. Cadence's Paul McLellan listens in as Jeremy ... » read more

Blog Review: Nov. 15
By Jesse Allen - 15 Nov, 2017 - Comments: 0

Cadence's Paul McLellan shares highlights from the Jasper User Group, including what to do when formal is not converging on a proof and formal in use at Arm. Synopsys' Anders Nordstrom explains how formal can verify SoC interconnects and get you from San Jose to Austin. Mentor's Jeff Miller argues that intelligent sensors are the basic building block for the IoT, and the market is growing... » read more

Which Verification Engine?
By Ed Sperling - 01 Nov, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

How To Handle Concurrency
By Brian Bailey - 30 Oct, 2017 - Comments: 3

The evolution of processing architectures has solved many problems within a chip, but for each problem solved another one was created. Concurrency is one of those issues, and it has been getting much more attention lately. While concurrency is hardly a new problem, the complexity of today’s systems is making it increasingly difficult to properly design, implement and verify the software an... » read more

Shhhhh… Deadlocks Anonymous In Session
By Rajesh Ramanujam - 26 Oct, 2017 - Comments: 0

I am sure there is an anonymous group – like Alcoholics Anonymous – headquartered in Silicon Valley, meeting every quarter to discuss the deadlocks that have paralyzed their products, roadmap and deployments. In discreet venues in every town, small groups of engineers huddle together to share war stories about the disgruntled customers whose trust was lost because of a deadlock discovered o... » read more

DVCon Europe Takes Over Munich October 16-17
By McKenzie Ross - 28 Sep, 2017 - Comments: 0

DVCon Europe is on the horizon, and this year's program should prove to be very timely. Chips and systems are getting more complex, verification is becoming more difficult, and formal has emerged as a critical piece of the verification suite The lineup this year tackles some key issues facing a changing semiconductor landscape. During a Monday tutorial, “Next Generation ISO 26262-based De... » read more

When Is Verification Complete?
By Ann Mutschler - 24 Aug, 2017 - Comments: 0

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This trend has been underway for the past couple of process nodes, but it takes time to spot trends and determine whether they are real or just aberrations. The Wilson Research Group conducts a ... » read more

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