tag: formal

Week In Review: Design, Low Power
By Jesse Allen - 26 Oct, 2018 - Comments: 0

Tools OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort. Synopsys released the latest ... » read more

Integrating Results And Coverage From Simulation And Formal
By Tom Anderson - 25 Oct, 2018 - Comments: 0

Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed enormous resources in terms of engineers, simulation ... » read more

AI Chips Must Get The Floating-Point Math Right
By Sergio Marchese - 27 Sep, 2018 - Comments: 0

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks today are often based on operations that use multiplication and addition of floating-point values, which subsequently need to be scaled to different sizes and for different needs. Modern FPGAs such as Intel Arria-10 ... » read more

Blog Review: Sept. 19
By Jesse Allen - 19 Sep, 2018 - Comments: 0

Applied Materials' David Thompson shares the new DARPA program that is focused on using correlated electrons to develop a new type of switch with quantum effects, potentially leading to unprecedented switching speeds. Mentor's Joe Hupcey III argues that for the most effective formal analysis, assertions should be as simple as possible and shares some tips on decomposing big assertions. Ca... » read more

Gaps In Verification Metrics
By Ann Mutschler - 23 Aug, 2018 - Comments: 0

As design complexity has exploded, the verification effort has likewise grown exponentially, with many different types of verification being applied to different classes of design. A recent panel discussion with leading chipmakers examined this topic in an effort to shed light on design health and quality, measuring the success of verification, knowing when verification is complete, being on... » read more

Bugs That Kill
By Brian Bailey - 23 Aug, 2018 - Comments: 3

Are simulation-resistant superbugs stifling innovation? That is a question Craig Shirley, president and CEO of Oski Technology, asked a collection of semiconductor executives over dinner. Semiconductor Engineering was invited to hear that discussion and to present the key points of the discussion. To promote free conversation, the participants, who are listed below, asked not to be quoted di... » read more

Functional Safety: Art Or Science?
By Sergio Marchese - 26 Jul, 2018 - Comments: 0

Nowadays, most hardware development projects deploy functional verification flows that include UVM-based constrained-random testbenches and formal verification. High design complexity, tough budget constraints, and short time to market are the norm, not the exception. Advanced verification is a necessity for many engineering teams. In our increasingly connected world, where billions of IoT devi... » read more

Verification As A Flow (Part 1)
By Brian Bailey - 05 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

The Skies Over EDA Are Finally Cloudy
By Tom Anderson - 28 Jun, 2018 - Comments: 0

EDA companies have been talking for years about providing access to their tools in the cloud, including more articles than I can count with titles about the EDA forecast being cloudy, clouds on the horizon, and so forth. The title of this post continues the dubious tradition of cloud-based puns, but there’s no future tense involved. Recent announcements from several EDA companies make it appe... » read more

Blog Review: June 27
By Jesse Allen - 27 Jun, 2018 - Comments: 0

Applied Materials' Sundeep Bajikar argues that to realize the full potential of AI, new computing architectures are necessary, otherwise AI will quickly become unaffordable. Synopsys' Iain Singleton considers why it may not always be necessary to start at the reset state during formal verification and how to use abstractions to get a head start on bug hunting. Cadence's Meera Collier look... » read more

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