What Goes Wrong In Advanced Packages


Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

Testing VCSEL Devices On-Wafer


Vertical-Cavity Surface-Emitting Lasers, or VCSELs, are seeing unparalleled demand, thanks to new uses for them in smartphone and automotive applications. 3D sensing for facial recognition is the key application in smartphones, with up to three VCSEL dies being integrated into a single phone. Emerging automotive applications such as driver monitoring, infotainment control and LiDAR will provide... » read more

Automotive IC Production Wafer Test In A Zero-Defect World


By Amy Leong, FormFactor. Innovations in automotive semiconductor ICs post a high bar for wafer test. FormFactor’s Chief Marketing Officer, Amy Leong, provides insights into the challenges associated with automotive IC production wafer testing amid the requirement for zero-defects. Click here to continue reading. » read more

Week In Review: Manufacturing, Test


OEMs and chipmakers In recent times, automotive companies have been impacted by chip shortages, forcing vendors to temporarily shutter their plants. OEMs are experiencing manufacturing disruptions due to semiconductor shortages as some semiconductor foundries allocate production, according to IDC. "Semiconductor content growth in vehicles continues to outpace vehicle unit sales growth, with gr... » read more

Testing Silicon Photonics In Production


As silicon photonics costs come down, the technology is being worked into new applications, from connectivity to AI. But full commercial production requires testing those photonic circuits before shipping them. Photonics testing is only getting started. Volume production is still not happening, and test equipment and techniques are still being developed. What exists today is a blend of exist... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Third Point, a hedge fund, released a letter, saying that Intel needs to explore its strategic alternatives. This includes the breakup of the chip giant. Obtained by Yahoo and others, the letter says Intel needs to decide “whether Intel should remain an integrated device manufacturer” and should divest certain failed acquisitions. Here’s another analysis of the sit... » read more

Week In Review: Manufacturing, Test


Chipmakers SMIC’s shares fell following the resignation of the company co-CEO, according to a report from Bloomberg. Liang Mong Song, co-CEO of the Chinese foundry company, has proposed to resign and the company has become aware of Liang’s intention of conditional resignation, according to a filing. A former technologist at TSMC and Samsung, Liang has opposed the appointment of a new board... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive Austin, Texas-based automotive startup Uhnder raised $45 million in Series C funding for its digital radar-on-chip. Telechips, a fabless semiconductor company that works on automotive SoCs, is using Arm’s IP to design its Dolphin5 SoC for ADAS (advanced drive assistance systems) and digital cockpits with in-vehicle infotainment (IVI). Dolphin5 will include the Arm’s Mali-G78A... » read more

3D NAND’s Vertical Scaling Race


3D NAND suppliers are accelerating their efforts to move to the next technology nodes in a race against growing competition, but all of these vendors are facing an assortment of new business, manufacturing, and cost challenges. Two suppliers, Micron and SK Hynix, recently leapfrogged the competition and have taken the scaling race lead in 3D NAND. But Samsung and the Kioxia-Western Digital (... » read more

Digital Test Bulks Up – Or Down


Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

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