Chip Industry Week In Review


Concerns mount on the use of American-manufactured semiconductors in Russian weapons, with Analog Devices, AMD, Intel and TI set to testify next week before the U.S. Senate Permanent Subcommittee on Investigations. Also, U.S. and other government agencies issued a joint advisory and more details about ongoing Russian military cyberattacks, espionage, and sabotage. The U.S. Commerce Departmen... » read more

Chip Industry Technical Paper Roundup: August 20


New technical papers recently added to Semiconductor Engineering’s library: [table id=252 /] More ReadingTechnical Paper Library home » read more

Dual Graphite-Gated BLG As Platform for Cryogenic FETs


A technical paper titled “Ultra-steep slope cryogenic FETs based on bilayer graphene” was published by researchers at RWTH Aachen University, Forschungszentrum Julich, National Institute for Materials Science (Japan), and AMO GmbH. "Here, we show that FETs based on Bernal stacked bilayer graphene encapsulated in hexagonal boron nitride and graphite gates exhibit inverse subthreshold slop... » read more

Research Bits: July 22


Sub-1nm gate Researchers from Korea's Institute for Basic Science, Sungkyunkwan University, Harvard University, and Korea Advanced Institute of Science and Technology (KAIST) found a method that enables epitaxial growth of 1D metallic materials with a width of less than 1 nm, which they used as a gate electrode of a miniaturized transistor. The team controlled the crystal structure of molyb... » read more

Chip Industry Technical Paper Roundup: April 30


These new technical papers were recently added to Semiconductor Engineering’s library. [table id=222 /] Find more technical papers here. » read more

Chip Industry Week In Review


SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

In-Memory Computing: Techniques for Error Detection and Correction


A new technical paper titled "Error Detection and Correction Codes for Safe In-Memory Computations" was published by researchers at Robert Bosch, Forschungszentrum Julich, and Newcastle University. Abstract "In-Memory Computing (IMC) introduces a new paradigm of computation that offers high efficiency in terms of latency and power consumption for AI accelerators. However, the non-idealities... » read more

Chip Industry Technical Paper Roundup: Feb. 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=187 /] More ReadingTechnical Paper Library home » read more

Heterogeneous Integration of Graphene and Hafnium Oxide Memristors Using Pulsed-Laser Deposition


A technical paper titled “Heterogeneous Integration of Graphene and HfO2 Memristors” was published by researchers at Forschungszentrum Jülich, Jožef Stefan Institute, and Jülich-Aachen Research Alliance (JARA-FIT). Abstract: "The past decade has seen a growing trend toward utilizing (quasi) van der Waals growth for the heterogeneous integration of various materials for advanced electro... » read more

Research Bits: May 16


Germanium-tin transistor Scientists at Forschungszentrum Jülich, CEA-Leti, University of Leeds, Leibniz Institute for High Performance Microelectronics, and RWTH Aachen University fabricated a new type of transistor from a germanium-tin alloy. Charge carriers can move faster in the material than in silicon or germanium, which enables lower voltages in operation. “The germanium–tin syst... » read more

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