tag: Fraunhofer IIS EAS

Optimizing Analog With Layout In The Loop
By Benjamin Prautsch - 15 May, 2025 - Comments: 0

Meeting high-performance requirements at low power isn’t easy. What is already challenging in digital is even more complex in analog. After specification and block-level system concept, the analog design flow typically spends considerable time coming up with well-working schematic-level topologies. However, once layout parasitics become apparent through parasitic extraction, the seemingly opt... » read more

Die-to-die Interconnect Standards In Flux
By Bryon Moyer - 15 May, 2025 - Comments: 0

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

Development Flows For Chiplets
By Brian Bailey - 15 May, 2025 - Comments: 2

Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary. Today, many companies have hit the reticle limit and are forced to move to multi-die solutions, but that does not create a plug-and-play chiplet market. These ear... » read more

Analog Creates Ripples in Digital Verification
By Brian Bailey - 24 Apr, 2025 - Comments: 0

We live in an analog world, but analog has been minimized whenever possible. At some point digital and analog must come together in every electronic device, and that has long been an area where errors creep in. The Wilson Research Group and Siemens EDA functional verification study has long shown that analog and mixed signal are two of the highest causes of flaws that result in chip respins.... » read more

Can Chiplets Serve Cost-Conscious Apps?
By Bryon Moyer - 17 Apr, 2025 - Comments: 0

Chiplets are emerging as a significant new phase in the evolution of the semiconductor market, providing a way to continue scaling performance well beyond the size limitations of a reticle. But that improvement comes with a high price tag and a lot more complexity, which so far has limited adoption. One of the main reasons for the cost increase is the need for advanced packaging when employi... » read more

Lego-Style Software For Automotive And Industrial Chiplet Systems?
By Andy Heinig - 10 Apr, 2025 - Comments: 0

Chiplets are a key topic in the semiconductor industry today, as they offer the potential to greatly increase the performance and flexibility of chips. The current focus is primarily on implementation, in particular on the architecture and the development of die-to-die interfaces that enable efficient communication between the individual chips. These technologies hold out the promise of meeting... » read more

Chiplet Tradeoffs And Limitations
By Ann Mutschler - 10 Apr, 2025 - Comments: 0

The semiconductor industry is buzzing with the benefits of chiplets, including faster time to market, better performance, and lower power, but finding the correct balance between customization and standardization is proving to be more difficult than initially thought. For a commercial chiplet marketplace to really take off, it requires a much deeper understanding of how chiplets behave indiv... » read more

What Exactly Are Chiplets And Heterogeneous Integration?
By Bryon Moyer - 20 Mar, 2025 - Comments: 1

The terms “chiplet” and “heterogeneous integration” fill news pages, conference papers, and marketing presentations, and for the most part engineers understand what they're reading. But speakers sometimes stumble during a presentation trying to figure out whether a particular die qualifies as a chiplet, and heterogeneous integration comes in different guises for different people. Both t... » read more

3D-IC For The Masses
By Brian Bailey - 13 Mar, 2025 - Comments: 1

The concepts of 3D-IC and chiplets have the whole industry excited. It potentially marks the next stage in the evolution of the IP industry, but so far, technical difficulties and cost have curtailed its usage to just a handful of companies. Even within those, they do not appear to be seeing benefits from heterogeneous integration or reuse. Attempts to make this happen are not new. "A decade... » read more

Chiplets Add New Power Issues
By Ann Mutschler - 13 Mar, 2025 - Comments: 0

Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors. Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors... » read more

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