tag: Fraunhofer IIS EAS

Mixed Messages Complicate Mixed-Signal
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Model-Based Systems Engineering
By Roland Jancke - 12 Jun, 2025 - Comments: 0

Today’s electronic systems are an increasingly complex combination of hardware and software components. They contain an ever-expanding range of functions, require more computing power, have to operate a wide variety of interfaces, comply with standards, and be compatible with established market solutions. Accommodating all the new functions and expanded capacity may require a larger silicon a... » read more

RISC-V’s Increasing Influence
By Brian Bailey - 12 Jun, 2025 - Comments: 2

The industry is increasingly talking about benefits brought by the RISC-V architecture, but is it even the right starting point? While it may not be perfect, it may provide the flexibility necessary to move forward gradually. Computer architectures and software have followed in the footsteps of processors developed 80 years ago. They aimed to solve sequential, scalar arithmetic problems usin... » read more

Multi-Die Assemblies Complicate Parasitic Extraction
By Ann Mutschler - 12 Jun, 2025 - Comments: 0

The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge. Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spik... » read more

The Best DRAMs For Artificial Intelligence
By Bryon Moyer - 12 Jun, 2025 - Comments: 0

Artificial intelligence (AI) involves intense computing and tons of data. The computing may be performed by CPUs, GPUs, or dedicated accelerators, and while the data travels through DRAM on its way to the processor, the best DRAM type for this purpose depends on the type of system that is performing the training or inference. The memory challenge facing engineering teams today is how to keep... » read more

Measurements and Simulation-Based Characterization Of eFuses
By Fraunhofer IIS/EAS - 11 Jun, 2025 - Comments: 0

In conventional safety systems, the off state can be assumed to be safe. With ADAS, this is no longer automatically the case. This makes it necessary to adopt new approaches to fuse protection, which will subsequently spread to other industries. Traditionally, the vehicle electrical system was protected by sacrificial fuses. These reliably disconnect the power supply in the event of overcurr... » read more

Challenges In Using Sub-7nm ICs In Automotive
By Laura Peters - 10 Jun, 2025 - Comments: 0

The automotive industry is producing vehicles with increasing levels of real-time decision-making, enabled by thousands of ICs, sensors, and multi-chip packages, but making sure these systems work flawlessly throughout their expected lifetimes is a growing challenge. Automotive chips traditionally were developed at mature process nodes in five- to seven-year cycles, but much has changed over... » read more

How Secure Are Analog Circuits?
By Ed Sperling - 05 Jun, 2025 - Comments: 0

The move toward multi-die assemblies and the increasing value of sensor data at the edge are beginning to focus attention and raise questions about security in analog circuits. In most SoC designs today, security is almost entirely a digital concern. Security requirements in digital circuits are well understood, particularly in large data centers and at the upper end of edge computing, which... » read more

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 1

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

Optimizing Analog With Layout In The Loop
By Benjamin Prautsch - 15 May, 2025 - Comments: 0

Meeting high-performance requirements at low power isn’t easy. What is already challenging in digital is even more complex in analog. After specification and block-level system concept, the analog design flow typically spends considerable time coming up with well-working schematic-level topologies. However, once layout parasitics become apparent through parasitic extraction, the seemingly opt... » read more

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