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Better Quality RTL


How do you measure the quality of RTL? Philippe Luc, director of verification at Codasip, talks about identifying bugs, improving the overall quality of the verification, what happens when different blocks are used in a design, and how to improve efficiency in the verification process. » read more

Bug Escapes And The Definition Of Done


National Semiconductor's design center (NSTA) in Herzliya was the place where I fell in love with chip verification. I joined the team in 1999, still during my BSc, and met a group of innovators with a passion to create great ASICs and improve the way we did it at all costs. It was fast-moving learning for me, both on the verification engineering and verification management sides of things. ... » read more

I’m Almost Done


The city of Belgrade is renovating the street where I live. They are also building a new building next to mine so that I can see the construction work from my balcony. Last week, they blocked the street for some 20 minutes, and people got out of their cars and waited outside for the road to open. The construction workers were not in a hurry, and it seemed like everyone was ok with that, so I... » read more

Confusion Persists In Verification Terms


I find it amazing that an area of technology that attempts to show, beyond a reasonable doubt, that a design will work before it is constructed can be so bad at getting some basic things right. I am talking about verification terminology. I have been in this industry for over 40 years and it is not improving. In fact, it is getting worse. The number of calls I have with people where they hav... » read more

Formal Signoff


Xiaolin Chen, senior AE at Synopsys, looks at what’s good enough coverage, what makes one assertion better than another, and where the potential holes are in verification. https://youtu.be/nBtKE0gDHBU » read more

Simplifying SystemVerilog Functional Coverage


Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly? This is where functional coverage comes in. SystemVerilog’s functional coverage constructs allow you to quantify the completeness of your stimulus by recording the values that... » read more

System Coverage Undefined


When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it's the one verification engineers lose sleep over. Exhaustive [getkc id="56" kc_name="coverage"] has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block... » read more

Full Coverage Or Full Monty


Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: Are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Tech Talk: Better Coverage


Atrenta's Yuan Lu talks about code coverage, functional coverage and the use of assertions in debugging designs. [youtube vid=Hpm-l1z8HTo] » read more

Measuring Verification Accuracy


[getkc id="10" kc_name="Verification"] is the unbounded challenge that continues to confound engineering teams across the globe, who want to know when "enough" is "good enough" to proceed to tapeout. The answer is not straightforward, and it includes more variables than in the past, particularly around power. Harry Foster, chief verification scientist at [getentity id="22017" e_name="Mentor ... » read more

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