Optimizing Tool Integration Is Essential To Design Success

By James Paris - 22 Dec, 2020 - Comments: 0

By James Paris and Armen Asatryan The relationship between a place and route (P&R) application and the collection of system-on-chip (SoC) design implementation, analysis, and verification methodologies and tools has always been very much a two-way street. The P&R system is the base, if you will, of design implementation—it takes the virtual and makes it physical. However, it is use... » read more

Rule Deck Comparison Doesn’t Have To Be Difficult

By Saunder Peng - 22 Jan, 2015 - Comments: 0

Foundry rule decks change all the time, as foundries uncover new manufacturing issues, or the process changes, or design criteria are tightened to improve runtime or stability. Sometimes new versions of a user’s design rule checking (DRC) tool are released, and the results from the DRC run differ from the previous version. Or perhaps a company wants to compare results between rule decks from ... » read more

It’s Time to Bring GDS “Reality” Into Routing Closure

By Jean-Marie Brunet - 17 Jul, 2014 - Comments: 0

By Nancy Nguyen and Jean-Marie Brunet Imported cells, whether macros, standard cells, or intellectual property (IP), are a common element of today’s integrated circuit (IC) designs. Historically, when designers incorporate these cells into a design, they import them using an abstract format defined by a layout exchange format (LEF) file. This abstract view provides basic information about th... » read more

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: GDS

Optimizing Tool Integration Is Essential To Design Success

Rule Deck Comparison Doesn’t Have To Be Difficult

It’s Time to Bring GDS “Reality” Into Routing Closure

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

Knowledge Centers
Entities, people and technologies explored